NXP Semiconductors MC9S12VRP64, Руководство владельца

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S12S Debug Module (S12DBGV2)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 217
6.4.2.1.2 Comparator B
Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is
set the access size (word or byte) is compared with the SZ bit value such that only the specified size of
access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are
shown in
Table 6-33 .
Access direction can also be used to qualify a match for Comparator B in the same way as described for
Comparator C in
Table 6-32 .
6.4.2.1.3 Comparator A
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
Table 6-34 lists access considerations with data bus comparison. On word accesses the data byte of the
lower address is mapped to DBGADH. Access direction can also be used to qualify a match for
Comparator A in the same way as described for Comparator C in
Table 6-32 .
Table 6-34. Comparator A Matches When Accessing ADDR[n]
Table 6-33. Comparator B Access Size Considerations
Condition For Valid Match Comp B Address RWE SZE SZ8 Examples
Word and byte accesses of ADDR[n] ADDR[n]
1
1
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
0 0 X MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Word accesses of ADDR[n] only ADDR[n] 0 1 0 MOVW #$WORD ADDR[n]
LDD ADDR[n]
Byte accesses of ADDR[n] only ADDR[n] 0 1 1 MOVB #$BYTE ADDR[n]
LDAB ADDR[n]
SZE SZ
DBGADHM,
DBGADLM
Access
DH=DBGADH, DL=DBGADL
Comment
0 X $0000 Byte
Word No databus comparison
0 X $FF00 Byte, data(ADDR[n])=DH
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match data( ADDR[n])
0 X $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match data( ADDR[n+1])
0 X $00FF Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL Possible unintended match
0 X $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data( ADDR[n], ADDR[n+1])
0 X $FFFF Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL Possible unintended match
1 0 $0000 Word No databus comparison
1 0 $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match only data at ADDR[n+1]
1 0 $FF00 Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match only data at ADDR[n]
1 0 $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data at ADDR[n] & ADDR[n+1]