NXP Semiconductors
UM10855
LPCXpresso board for LPC54100 family of MCUs
UM10855_OM1377.docm
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© NXP B.V. 2014. All rights reserved.
User manual
Rev. 1.0
— 4th November 2014
5 of 19
Designator
Description
Reference
section
J4
LPC54102 Target Power input. Connect this micro USB B-
type connector to a +5V power source when it is desired to
power only the LPC54102 Target, and leave the on-board
Link2 debug probe unpowered. This is useful when an
external debug probe is used to debug the LPC54102
Target.
J3
PMod™ (SPI / I
2
C) Bridge connector. An external
Application Processor (AP)
or PMod™ peripheral may be
connected to the LPC54102 Target MCU SPI0 and I2C2 via
this connector.
J5
FTDI serial header. In addition to provide a serial output
from LPC54102, the Target side of the board can be
powered from the FTDI header. The LPC54102 supports
serial ISP boot from the FTDI header.
J6
Link2 micro USB B-type connector. Powers both the Link2
side of the board and LPC54102 Target side of the board.
Power the board from this connector when using the on-
board debug probe to debug the LPC54102 Target MCU.
JP1
LPC54102 Target SWD disable
– 2-position jumper pins.
1) Jumper open (
default
) the LPC54102 Target SWD
interface enabled. Normal operating mode where
the Target SWD is connected to either the on-board
Link2 debug probe or an external debug probe.
2) Jumper shunted, the LPC54102 Target SWD
interface is disabled. Use this setting only when the
on-board Link2 debug probe is used to debug an
off-board Target MCU.
JP2
SWD VREF power selection
– 3 position jumper pins.
1) Jumper 1
– 2 (
default
) when on-board LPC54102
Target is connected to either the on-board Link2
debug probe or an external debug probe.
2) Jumper 2
– 3 when on-board Link2 debug probe is
used to debug an off-board Target MCU.
JP3
An alternate value voltage sense resistor may be installed
across JP3 terminals. By default JP3 is shunted by a 0Ω
resistor installed at JS5. Remove the shunt at JS5 to use
an alternate voltage sense resistor.
JP4
A current meter may be installed across JP4 terminals to
measure the LPC54102 current consumption. By default
JP4 is shunted by a 0Ω resistor installed at JS6. Remove
the shunt at JS6 to measure current at JP4.
JP5
Link2 (LPC43xx) force DFU boot
– 2 position jumper pins.
1) Jumper open (
default
) for Link2 to follow the normal
boot sequence. The Link2 will boot from internal
flash if image is found there. With the internal flash
erased the Link2 normal boot sequence will fall
through to DFU boot.
2) Jumper shunted to force the Link2 to DFU boot
mode. Use this setting to reprogram the Link2
internal flash with a new image or to use the
LPCXpresso IDE with Redlink protocol.