NXP Semiconductors LPC800, Руководство пользователя

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 77 of 313
NXP Semiconductors
UM10601
Chapter 7: LPC800 GPIO port
7.6 Register description
The GPIO port registers and the GPIO pin interrupt registers are located on the ARM M0+
I/O port. The I/O port supports single-cycle access.
Remark:
In all GPIO registers, bits that are not shown are reserved.
GPIO port addresses can be read and written as bytes, halfwords, or words.
“ext” indicates that the data read after reset depends on the state of the pin, which in turn
may depend on an external source.
7.6.1 GPIO port byte pin registers
Each GPIO pin has a byte register in this address range. Software typically reads and
writes bytes to access individual pins, but can read or write halfwords to sense or set the
state of two pins, and read or write words to sense or set the state of four pins.
7.6.2 GPIO port word pin registers
Each GPIO pin has a word register in this address range. Any byte, halfword, or word read
in this range will be all zeros if the pin is low or all ones if the pin is high, regardless of
direction, masking, or alternate function, except that pins configured as analog I/O always
read as zeros. Any write will clear the pin’s output bit if the value written is all zeros, else it
will set the pin’s output bit.
Table 68. Register overview: GPIO port (base address 0xA000 0000)
Name Access Address
offset Description Reset
value Width Reference
B0 to B17 R/W 0x0000 to 0x0012 Byte pin registers port 0; pins
PIO0_0 to PIO0_17 ext byte (8 bit) Table 69
W0 to W17 R/W 0x1000 to 0x1048 Word pin registers port 0 ext word (32 bit) Table 70
DIR0 R/W 0x2000 Direction registers port 0 0 word (32 bit) Table 71
MASK0 R/W 0x2080 Mask register port 0 0 word (32 bit) Table 72
PIN0 R/W 0x2100 Port pin register port 0 ext word (32 bit) Table 73
MPIN0 R/W 0x2180 Masked port register port 0 ext word (32 bit) Table 74
SET0 R/W 0x2200 Write: Set register for port 0
Read: output bits for port 0 0 word (32 bit) Table 75
CLR0 WO 0x2280 Clear port 0 NA word (32 bit) Table 76
NOT0 WO 0x2300 Toggle port 0 NA word (32 bit) Table 77
Table 69. GPIO port 0 byte pin registers (B[0:17], addresses 0xA000 0000 (B0) to 0xA000
0012 (B17)) bit description
Bit Symbol Description Reset
value Access
0 PBYTE Read: state of the pin PIO0_n, regardless of direction,
masking, or alternate function, except that pins configured as
analog I/O always read as 0.
Write: loads the pin’s output bit.
ext R/W
7:1 Reserved (0 on read, ignored on write) 0 -