NXP Semiconductors LPC43Sxx, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 27 of 1441
2.1 How to read this chapter
The ARM Cortex-M0APP processor is available on all LPC43xx/LPC43Sxx parts.
The ARM Cortex-M0SUB subsystem core is only available on parts LPC437x/LPC43S7x
and LPC436x/LPC43S6x parts only.
2.2 Basic configuration
The ARM Cortex-M0 processor(M0APP) is configured as follows:
•
See Table 5 for clocking and power control.
•
The ARM Cortex-M0 is reset by the M0APP_RST (reset #56) or by a general Reset.
•
After power-up, the ARM Cortex-M0 remains in reset until the reset is released by
clearing the corresponding RESET_CTRL1 bit (see
Table 173 ).
•
The ARM Cortex-M0 interrupt is connected to interrupt slot # 1 in the ARM Cortex-M4
NVIC and slot #31 in the ARM Cortex-M0SUB. See
Table 79 for peripheral interrupts
connected to the ARM Cortex-M0APP.
•
To clear the ARM-Cortex-M0 interrupt, use the M0APPTXEVENT register ( Table 110 ).
See Section 2.4.2 .
The ARM Cortex-M0 subsystem core (M0SUB) is configured as follows:
•
See Table 5 for clocking and power control.
•
The ARM Cortex-M0 subsystem core is reset by the M0SUB_RST (reset # 12) or by a
general Reset.
•
After power-up, the ARM Cortex-M0 subsystem core remains in reset until the reset is
released by clearing the corresponding RESET_CTRL0 bit (bit 12, see
Table 172 ).
•
The ARM Cortex-M0 subsystem core interrupt is connected to interrupt slot # 50 in
the ARM Cortex-M4 NVIC and interrupt slot #31 in the ARM Cortex-M0APP NVIC.
See
Table 80 for peripheral interrupts connected to the ARM Cortex-M0 subsystem
core.
•
To clear the ARM-Cortex-M0 interrupt, use the M0SUBTXEVENT register ( Table 109 ).
See Section 2.4.2 .
UM10503
Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and
Inter-Process Communication (IPC)
Rev. 2.1 — 10 December 2015 User manual
Table 5. ARM Cortex-M0 clocking and power control
Base clock Branch clock Operating
frequency
ARM Cortex-M0 clock (to the
M0APP core) BASE_M4_CLK CLK_M4_M0 up to 204 MHz
ARM Cortex-M0 subsystem clock
(to the M0SUB core) BASE_PERIPH_CLK CLK_CLK_PERIPH
_CORE up to 204 MHz