NXP Semiconductors LPC43Sxx, Руководство пользователя

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User manual Rev. 2.1 — 10 December 2015 230 of 1441
NXP Semiconductors
UM10503
Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)
15.4.1 RGU reset control register
The RGU reset control register allows software to activate and clear individual reset
outputs. Each bit corresponds to an individual reset output, and writing a one activates
that output. The reset output is automatically de-activated after a fixed reset delay period
with the exception of the M0APP_RST. If the reset output has a manual release, it stays
activated once pulled low until a 0 is written to the appropriate bit in this register. This
applies whether the reset activation came from the Reset Control Register or any other
source.
Remark: The reset delay is counted in IRC clock cycles. If the core frequency CCLK is
much higher than the IRC frequency, add a software delay of f
CCLK
/f
IRC
clock cycles
between resetting and accessing any of the peripheral blocks.
RESET_EXT_STAT55 R/W 0x4DC Reset external status register 55 for
CAN0_RST 0x4 see Table 183
RESET_EXT_STAT56 R/W 0x4E0 Reset external status register 56 for
M0APP_RST 0x8 see Table 184
RESET_EXT_STAT57 R/W 0x4E4 Reset external status register 57 for
SGPIO_RST 0x4 see Table 183
RESET_EXT_STAT58 R/W 0x4E8 Reset external status register 58 for
SPI_RST 0x4 see Table 183
RESET_EXT_STAT59 - 0x4EC Reserved - -
RESET_EXT_STAT60 R/W 0x4F0 Reset external status register 60 for
ADCHS_RST 0x4 see Table 183
RESET_EXT_STAT61 - 0x4F4 Reserved - -
RESET_EXT_STAT62 - 0x4F8 Reserved - -
RESET_EXT_STAT63 - 0x4FC Reserved - -
Table 171. Register overview: RGU (base address: 0x4005 3000)
…continued
Name Access Address
offset Description Reset value Reference
Table 172. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description
Bit Symbol Description Reset
value Access
0 CORE_RST Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle. 0 W
1 PERIPH_RST Writing a one activates the reset. This bit is automatically cleared to 0
after three clock cycles. 0 W
2 MASTER_RST Writing a one activates the reset. This bit is automatically cleared to 0
after three clock cycles. 0 W
3 - Reserved 0 -
4 WWDT_RST Writing a one to this bit has no effect. 0 -
5 CREG_RST Writing a one to this bit has no effect. 0 -
6 - Reserved 0 -
7 - Reserved 0 -
8 BUS_RST Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle. Do not use during normal operation 0 W