UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
12 of 1269
2.1 How to read this chapter
The ARM Cortex-M0 co-processor is available on all LPC43xx parts.
2.2 Basic configuration
The ARM Cortex-M0 co-processor is configured as follows:
•
See
for clocking and power control.
•
The ARM Cortex-M0 is reset by the M0APP_RST (reset # 56) or by a general Reset.
•
After power-up, the ARM Cortex-M0 reset must be released by clearing the
corresponding RESET_CTRL1 bit (see
).
•
The ARM Cortex-M0 interrupt is connected to interrupt slot # 1 in the ARM Cortex-M4
NVIC. See
for peripheral interrupts connected to the ARM Cortex-M0.
•
To clear the ARM-Cortex-M0 interrupt, use the M0TXEVENT register (
). See
.
2.3 Introduction
The LPC43xx is a dual-core microcontroller implementing an ARM Cortex-M4 and an
ARM Cortex-M0 core. The ARM Cortex-M4 is used as application processor. The second
core, the ARM Cortex-M0, can be used as co-processor to off-load the ARM Cortex-M4
and to perform serial I/O tasks. A communication protocol between the two processors is
needed. This chapter describes the Inter Process Communication (IPC) protocol for the
LPC43xx.
2.4 General description
On the LPC43xx, the ARM Cortex-M4 host CPU is used as the top-level system controller.
The LPC43xx also includes a second CPU, an ARM Cortex-M0. The ARM Cortex-M0
CPU is controlled by the host CPU. The communication between both CPUs makes use
of shared memory space and interrupts.
UM10503
Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter-
Process Communication (IPC)
Rev. 1.3 — 6 July 2012
User manual
Table 5.
ARM Cortex-M0 clocking and power control
Base clock
Branch clock
Operating frequency
ARM Cortex-M0 clock
BASE_M4_CLK
CLK_M4_M0
up to 204 MHz
