NXP Semiconductors KIT-TPLSNIFEVB, Руководство пользователя

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NXP Semiconductors
UM11650
KIT-TPLSNIFEVB tool
• The USB Micro-B connector: to connect to a 5.0 V source. It is labeled J4 in the
schematics.
Figure 6. Power and data connectors
5.2.1 Connecting to the logic analyzer
The data output connector (J3) is an 8-pin 4x2 male connector used as an interface to
the logic analyzer, to transfer TPL messages converted to SPI format.
The signals are all unidirectional and their direction is from the TPL sniffer (output) to the
logic analyzer (input).
The TPL sniffer is designed such that the cable connection to the logic analyzer can
be relatively long, with a maximum length of 2 m, without loss of signal integrity and
therefore maintaining the logic and timing information.
This statement is only true if the following two rules are both satisfied:
• The cable used for the connection must have a characteristic impedance of 100 Ω. This
is the impedance normally found on standard IDC ribbon cables.
• The logic analyzer side of the cable should only be loaded with high impedance
terminations such as a High-Z input from an oscilloscope, for example, 15 pF || 1 MΩ,
or 5 pF || 10 MΩ (better), or digital inputs from a logic analyzer (for example, 10 pF || 2
MΩ).
Failure to follow these rules does not guarantee proper operation of the TPL sniffer,
unless the cable length is considerably short (< 15 cm) so that reflections in the cable can
be neglected.
For signal integrity and EMI reduction, the data lines are interleaved with the ground
potential with the pinout described in Table 1 .
The TPL sniffer data output lines and the TPL inputs are internally protected by ESD
suppression devices. Nevertheless, standard electrostatic precautions should be taken
when handling and using the TPL sniffer.
The pin assignment for the data output connector is described in the following table:
Pin Signal Description
1 INTB SPI interrupt signal
2 GND Ground
3 RXCLK SPI bus clock
4 GND Ground
5 RXDATA SPI bus data
Table 1. ANALYZER connector (J3) pin assignment
UM11650 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1 — 4 August 2021
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