MCIMX6Q-SL: Development platform for i.MX 6Quad
Built to Freescale®
SABRE Lite design
Doc ID: MCIMX6QSLUM
Rev. 0.9, 11/12/2012
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5
USB2_VBUS
+5V
6
USB2_D-
USB Data-
7
USB Data+
8
GND
GND
Table 3-12 USB Host Interface
J1
Pin
Signal
Function
1
5VIN
+5V
2
USBDN_DM3
USB Data-
3
USBDN_DP3
USB Data+
4
GND
GND
3.3.12
Micro USB Interface
The micro connector is connected to the high-speed (HS) USB 2.0 OTG module of the i.MX 6 processor and is
cross connected with the lower USB Host port on J3. When a 5V supply is seen on the micro connector (from
the USB Host), the i.MX 6Q processor will configure the OTG module for device mode, which will prevent the
lower USB Host port from operating correctly.
Figure 3-11 Micro USB Interface
Table 3-13 Micro USB Interface
J3
Pin
Signal
Function
1
USB0_VBUS
+5V
2
USB0_D-
USB Data-
3
USB Data+
4
ID
USB ID
5
GND
GND