MCIMX6Q-SL: Development platform for i.MX 6Quad
Built to Freescale®
SABRE Lite design
Doc ID: MCIMX6QSLUM
Rev. 0.9, 11/12/2012
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Table 3-5 Parallel RGB interface
J15
Pin
Signal
Function
1
GND
GND
2
GND
GND
3
GND
GND
4
DISP0_CNTRST
GPIO
5
R0
DISP0 data bit16
6
R1
DISP0 data bit17
7
R2
DISP0 data bit18
8
R3
DISP0 data bit19
9
R4
DISP0 data bit 20
10
R5
DISP0 data bit 21
11
R6
DISP0 data bit 22
12
R7
DISP0 data bit 23
13
G0
DISP0 data bit 8
14
G1
DISP0 data bit 9
15
G2
DISP0 data bit10
16
G3
DISP0 data bit 11
17
G4
DISP0 data bit 12
18
G5
DISP0 data bit 13
19
G6
DISP0 data bit 14
20
G7
DISP0 data bit 15
21
B0
DISP0 data bit 0
22
B1
DISP0 data bit 1
23
B2
DISP0 data bit 2
24
B3
DISP0 data bit 3
25
B4
DISP0 data bit 4
26
B5
DISP0 data bit 5
27
B6
DISP0 data bit6
28
B7
DISP0 data bit 7
29
GND
GND
30
DISP0_CLK
Pixel Clock
31
GND
GND
32
DISP0_HSYNC
DISP0 HSYNC
33
DISP0_VSYNC
DISP0 VSYNC
34
DISP0_DRDY
DISP0 enable chip select
35
I2C3_SCL
IIC master serial clock,