UARTx_C4 field descriptions
Field
Description
7
MAEN1
Match Address Mode Enable 1
See
for more information.
0
All data received is transferred to the data buffer if MAEN2 is cleared.
1
All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA1 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer.
6
MAEN2
Match Address Mode Enable 2
See
for more information.
0
All data received is transferred to the data buffer if MAEN1 is cleared.
1
All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA2 register. If no match occurs, the data is
discarded. If a match occurs, data is transferred to the data buffer.
5
M10
10-bit Mode select
Causes a tenth, non-memory mapped bit to be part of the serial transmission. This tenth bit is generated
and interpreted as a parity bit. The M10 field does not affect the LIN send or detect break behavior. If M10
is set, then both C1[M] and C1[PE] must also be set.
See
for more information.
0
The parity bit is the ninth bit in the serial transmission.
1
The parity bit is the tenth bit in the serial transmission.
BRFA
Baud Rate Fine Adjust
This bit field is used to add more timing resolution to the average baud frequency, in increments of 1/32.
See
46.4.12 UART Control Register 5 (UARTx_C5)
Address: Base a Bh offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
UARTx_C5 field descriptions
Field
Description
7
TDMAS
Transmitter DMA Select
Configures the transmit data register empty flag, S1[TDRE], to generate interrupt or DMA requests if
C2[TIE] is set.
NOTE:
• If C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are not asserted
when the TDRE flag is set, regardless of the state of TDMAS.
• If C2[TIE] and TDMAS are both set, then C2[TCIE] must be cleared, and D must not be
written unless a DMA request is being serviced.
Table continues on the next page...
Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1285
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