Table 3. Default DIP switch configurations (continued)
Switch
Default setting
[OFF = 0, ON = 1]
Switch name
Description
The manual switching from the REF_SEL pin is disabled by
default in the AD9525. For more details, see
section 3.1.1
of
the
AD9525 Data Sheet
.
NOTE: Freescale Semiconductor, Inc. does not own the
AD9525 Data Sheet
and it is mentioned solely for
reference purposes.
SW5[7]
OFF
NOR_VBANK0
Modifies the NOR flash addressing. Leave the switches OFF.
SW5[6]
OFF
NOR_VBANK1
SW5[5]
OFF
BIV_MODE
Enables the boot image validation. It determines whether the
boot image must be validated.
OFF: Boot image validation is disabled.
ON: Boot image validation is enabled.
SW5[4]
OFF
SER_DL_SEL
Maps to the SER_DL_SEL switch of the AFD4400. It selects
the serial boot interface (valid only when IPC_TYP boots from
the serial communication interface).
OFF: Boots from UART (if IPC_TYP is OFF).
ON: Boots from Ethernet (if IPC_TYP is OFF).
SW5[3]
OFF
IPC_TYP
Maps to the IPC_TYP switch of the AFD4400. It enables the
IPC boot mode through a serial communication interface.
OFF: Boots from the serial communication interface.
ON: Reserved for other interfaces of future products.
SW5[2]
OFF
BOOT_MODE1
Maps to the BMOD[1:0] pins of the AFD4400 processor and
select the boot source.
OFF OFF: The read only memory (ROM) code reads image
from the external parallel flash through WEIM.
OFF ON: Boots from the inter-processor communication (IPC)
through the serial interface.
ON OFF: Boots from the external NOR device through the
wireless external interface module (WEIM) interface.
ON ON: Freescale Test mode.
SW5[1]
OFF
BOOT_MODE0
SW6[8]
ON
BRD_EEPROM_WP
Connects to the write protect of I2C EERPOM.
OFF: I2C EEPROM write protection is disabled.
ON: I2C EEPROM write protection is enabled.
SW6[7]
ON
SPARE_BYP1
Spare
SW6[6]
ON
RESET_PG_BYPASS_
B
Connects the 1.8 V regulator and DDR3 VTT regulator with a
power good (PG) function to RSTIN of the AFD4400.
OFF: No control on RSTIN_B de-assertion.
ON: RSTIN_B is de-asserted only when the secondary 1.8 V
power supply and DDR3 VTT regulator PG is asserted.
SW6[5]
ON
VSEC_1V5_BYPASS_B Connects the core supply regulator PG to enable the
secondary 1.5 V power supply.
Table continues on the next page...
Default switch settings
AFD4400 Reference Design Board Quick Start, Rev. 0, 07/2015
Freescale Semiconductor, Inc.
13
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