DSP56858EVM User Manual, Rev. 3
2-18
Freescale Semiconductor
about to start. The FSYNC frequency is always the system’s sample rate. It may be an input to
the codec, or it may be an output from the codec in data mode.
The basic codec digital connections are shown in
Figure 2-12
,
Table 2-9
and
Table 2-10
.
The codec’s MODE is set by the three MODE selection resistors, R42-R44. In the factory default
setting of MODE 4, the codec is set to be the master of the ESSI bus with its data word set at 32
bits per frame; i.e., 16 bits Left channel and 16 bits Right channel. The sample rate is selected on
the Sample Rate Selector switch S5; see
Table 2-8
for selection options. Codec control
information is sent over a separate serial port using: PC3 as the Control Chip Select signal, CCS;
PE2 as the Control Data Input signal, CDIN; and PE3 as the Control Clock signal, CCLK.
CODEC Enable Logic
56858
CS4218
SDIN
SDOUT
SCLK
FSYNC
RESET
STD0
SRD0
SCK0
SC02
PC4
CCS
CDIN
CCLK
PC3
PE2
PE3
1
3
5
7
9
2
4
6
8
10
1
3
5
2
4
6
JG6
JG7
Figure 2-12. CS4218 Stereo Audio Codec
Table 2-9. ESSI Port Connector Description
JG6
Pin #
Controller Signal
Pin #
Codec Signal
1
STD0
2
SDIN
3
SRD0
4
SDOUT
5
SCK0
6
SCLK
7
SC02
8
FSYNC
9
PC4
10
RESET
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