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Stereo Codec
Technical Summary, Rev. 3
Freescale Semiconductor 2-17
2.12.1 Analog Input/Output
The 56858EVM uses jacks for line-level stereo input, line-level stereo output and stereo
headphone output. A National Semiconductor LM4880 provides the drive required for the use of
headphones. This device offers a THD, which is superior by a factor of two to the CS4218’s
on-chip headphone drive circuitry. The basic Analog codec connections are shown in
Figure 2-11
.
Line-Level
Output
RIN1
LIN1
LOUTL
LOUTR
A
A
A
Line-Level
Output
Headphone
Input
CS4218
LM4880
P4 P5
P6
Figure 2-11. CODEC Analog Connections
2.12.2 Digital Interface
The serial interface of the codec transfers digital audio data and control data into and out of the
device. The ESSI port consists of independent transmitter and receiver sections and is used for
serial communication with the codec.
On the controller side, the Serial Transmit Data pin, STD0, is an output when data is being
transmitted to the codec. The Serial Receive Data pin, SRD0, is an input when data is being
received from the codec. These two pins are connected to the codec’s Serial Data Input, SDIN,
and Serial Data Output, SDOUT, pins.
The controller’s Transmit Serial Clock pin, SCK0, provides the serial bit rate clock for the ESSI
interface. It is connected to the CODEC’s Serial Port Clock pin, SCLK. Data is transmitted on the
rising edge of SCLK and is received on the falling edge of SCLK.
The controller’s GPIO PORT C Bit 4 pin, PC4, is programmed to control the codec’s Active Low
Reset signal, RESET.
The Serial Transmit Frame Sync pin, SC02, is programmed to control the codec’s Frame Sync
signal, FSYNC. This signal is sampled by SCLK, with a rising edge indicating a new frame is