NVIDIA nForce 590 SLI Technology Chipset Overclocking
DU-02451-001_v01
4
05/17/06
t
RRD
RAS to RAS Delay is the amount of cycles that it takes to activate
the next bank of memory. The lower the timing, the better the
performance but it can cause instability.
t
REF
Refresh Rate is the amount of time it takes before a change is
refreshed. If the charge is not refreshed enough, the signal loses
its charge and corrupts data. It is measured in microseconds.
t
RP
Row Precharge time is the minimum time between active
commands and the read/writes of the next bank of the memory
module.
t
RWT
Read to Write Delay is when a write command is received, this is
the amount of cycles for the command to be executed.
t
RDRD
Read to Read Timing is the number of clock cycles between the
last read and the subsequent READ command to the same
physical bank.
t
RC
Row Cycle time is the minimum time in cycles it takes a row to
complete a full cycle. This can be determined by
t
RC
=
t
RAS
+
t
RP
.
If
t
RC
is set too short, it can cause data corruption. If
t
RC
is set too
long, stability increases at the expense of performance.
t
WTR
Write to Read Delay is the amount of cycles required between a
valid write command and the next read command. Lower is
better performance but can cause instability.
t
WRWR
Write to Write time is the number of clock cycles between the last
write and the subsequent WRITE command to the same physical
bank.
t
CL
CAS latency is the number of clock cycles between the memory
receiving a
READ
command and actually starting to read
t
CPC
Command per Clock has only two values: 1 and 2. When set to 1,
it provides the best performance but limits memory frequency. In
order to overclock memory frequency, a value of 2 is more
reasonable.
