NANO100
Feb. 26, 2018
Page
8
of 18
Rev 1.00
NUT
INY
-S
DK
-N
A
NO
1
00
U
S
E
R
M
A
NUA
L
49
PD.7
113
XT1_IN
50
PD.14
114
XT1_OUT
51
PD.15
115
NC
52
PC.5/SPI0_MOSI1
116
nRESET
53
PC.4/SPI0_MISO1
117
VSS
54
PC.3/SPI0_MOSI0/I2S_DO/SC1_RST
118
VSS
55
PC.2/SPI0_MISO0/I2S_DI/SC1_PWR
119
NC
56
PC.1/SPI0_CLK/I2S_BCLK/SC1_DAT
120
VDD
57
PC.0/SPI0_SS0/I2S_LRCLK/SC1_CLK
121
NC
58
PE.6
122
PF.4/I2C0_SDA
59
NC
123
PF.5/I2C0_SCL
60
NC
124
VSS
61
PE.5/PWM1_CH1
125
PVSS
62
PB.11/PWM1_CH0/TM3/SC2_DAT/SPI0
_MISO0
126
PB.8/STADC/TM0/INT0/SC2_PWR
63
PB.10/SPI0_SS1/TM2/SC2_CLK/SPI0_
MOSI0
127
PE.15
64
PB.9/SPI1_SS1/TM1/SC2_RST/INT0
128
PE.14
Table 2-1 Pin Assignment for NANO100
