Nuvoton ISD2360, Руководство по конструкции, Страница: 38 / 72

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 31 - Revision v1.14
Figure 7-3 Sample_Project_2 Configuration
The following exlpains the POI VM:
CFG( REG2, 0x44)

write 0x44 into reg0x02; enable Decoder and PWM output path;
CFG( VOLC, 0x04)

write 0x04 into reg0x03; set attenuation at 4*(-0.25)dB value;
PLAY(FastBeep)
 Play VP ―Fastbeep‖
CFG( REG_GPIO_OE, 0x00)

write 0x00 into reg0x1A; configure all GPIO pins as input pins;
CFG( REG_GPIO_PE, 0x3F)

write 0x3F into reg0x1B; enable Pull-Enable for GPIO0-5;
CFG( REG_GPIO_PS, 0x3F)

write 0x3F into reg0x1D; enable Pull-High for GPIO0-5;
CFG( REG_GPIO_AF1, 0x37)

write 0x37 into reg0x1E;
CFG( REG_GPIO_AF0, 0x00)

write 0x00 into reg0x1F; combined with reg0x1E to confiure GPIO0,1,2,
4 and 5 as falling edge triggering pins.
CFG(GPIO_TRIG_CH_SEL_L, 0x24)

write 0x24 into reg0x14, assign channel 0 to VM associated with GPIO0;
assign channel 1 to VM associated with GPIO1;
assign channel 2 to VM associated with GPIO2;
assign channel 0 to VM associated with GPIO3;
CFG(GPIO_TRIG_CH_SEL_H, 0x03)

write 0x03 into reg0x15, assign all channels to VM associated with GPIO4;
assign channel 0 to VM associated with GPIO5;
CFG(GPIO_VOL_UD_SEL, 0x03)

write 0x03 into reg0x16, GPIO4 Trigger to volume up;
GPIO5 trigger to volume down;
CFG( R0, 0x03)

write 0x03 into reg0x20; associate VM0x03 with GPIO0;
CFG( R1, 0x04)

write 0x04 into reg0x22; associate VM0x04 with GPIO1;
CFG( R2, 0x05)

write 0x05 into reg0x24; associate VM0x05 with GPIO2;
CFG( R3, 0x06)

write 0x06 into reg0x26; associate VM0x06 with GPIO3;
CFG( R4, 0x07)

write 0x07 into reg0x28; associate VM0x07 with GPIO4;
CFG( R5, 0x08)

write 0x08 into reg0x2A; associate VM0x08 with GPIO5;
PD

power down device (to save power).
As in Sample_Project_1, the initial status and trigger conditions are set in Sample_Project_2.
Other functions are set in Sample_Project_2 as well: Input mode is set with internal pull high
by the
Output Enable Control Register , the Pull Select Control Register and the Pull Enable
Control Register ; GPIO pin trigger mode is set by the Alternate Function Control 1 and
Alternate Function Control 0 registers; assignment of the trigger channel(s) is set by the GPIO
Trigger Channel Select 1 and GPIO Trigger Channel Select 2 registers; and assignment of
the associated VM indexes is performed.