CODEC Motherboard Manual Version 1.3
Page 31 of 66
April 12, 2016
CODEC Motherboard
13.8
Digital Audio Control
Figure 17: DAC/PLL/DIGITAL AUDIO PANEL
– DIGITAL AUDIO CONTROL
13.9
Clock Generation Control
The Clock Generation Control block sets up the relationship of the ADC and DAC to the FS and
BLCK digital audio data bus signals. It is important to understand carefully the detailed
information regarding this, which is in the PLL description in the NAU8822 Design Guide.
As mentioned in the heading of this section, the details of all of the functions and bits are
described in detail in the NAU8822 design guide and appendices. The bit names match this
documentation, and using a text string search in the Design Guide is a good method to quickly
locate specific information about a specific control bit function.
13.10
CLKIOEN Master Mode
Selecting this control bit will cause NAU8822 device to drive the FS and BCLK pins as the master
of the I2S or PCM digital audio data bus. If this is not selected, the NAU8822 device will be the
slave of the digital audio data bus and the FS and BLCK pins will be used as inputs to the
NAU8822 device.
