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WAAS GUS Signal Generator User Guide Rev 1
Chapter 5
Messages
RF CIRCUIT FAULT FIELD
This flag indicates if the RF circuit board is faulty. If a ‘1’, then the RF circuit board is faulty. If a ‘0’, then the RF
circuit board is not faulty.
BPSK OR QPSK MODE SELECTED
This flag indicates the modulation mode selected, BPSK or QPSK. If set to '0', then BPSK modulation mode is
selected. If set to '1', then QPSK mode is selected. The value of this flag is determined by the BPSK/QPSK
Modulation Mode Select bit, see
Table 13, L1/L5 Control Command Bit Fields
SYMBOLS PER SECOND FIELD
This flag indicates the hardware symbol rate. If a ‘0’, then the Signal Generator is processing 500 symbols per
second. The Symbol Rate field in the L5 Initialization Command determines the value of this flag, see
Initialization Command Fields 500 SPS
.
SIGNAL GENERATOR OPERATIONAL
This flag indicates if the Signal Generator is operational and that Code Rate Commands and Carrier Frequency
Commands are accepted. If this bit is set to ‘0’, Code Rate Commands and Carrier Frequency Commands are not
applied. If this bit is set to ‘1’, the Signal Generator is operational and Code Rate Commands and Carrier Frequency
Commands are applied. This bit is only set to ‘0’ at power-up and after a Reset Command is received. It is set to ‘1’
after a Control Command is received and all internal calibrations have been performed.
REFERENCE 1PPS PRESENT FIELD
The flag indicates if the 1PPS reference is present. If this bit is set to ‘1’, the 1PPS signal is present. If this bit is set
to ‘0’, the 1PPS signal is not present.
5.1.4.7
Reset Command Second Epoch Counter
This field contains the number of one second epochs counted since the last hardware reset occurred or since the last
RESET command was received. The counter is started upon successful detection of an external 1PPS update pulse.
The range of this field is 0 – (2
31
-1). The MSB is set to zero to prevent false detection of packet SYNC header
bytes.
shows the byte order and format for this field.
Table 43: Reset Command Second Epoch Counter
5.1.4.8
Hardware Reset Second Epoch Counter
This field contains the number of one second epochs counted since the last hardware reset occurred. The counter is
started upon successful detection of an external 1PPS update pulse. The range of this field is 0 – (2
31
-1). The MSB
is set to zero to prevent false detection of packet SYNC header bytes.
shows the byte order and
format for this field.
Table 44: Hardware Reset Second Epoch Counter
LS Byte [16]
D0 = LSB
Byte [17]
Byte [18]
LS Byte [19]
D31 = MSB = ‘0’
D7 – D0
D15 – D8
D23 – D16
D31 – D24
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
LS Byte [20]
D0 = LSB
Byte [21]
Byte [22]
LS Byte [23]
D31 = MSB = ‘0’
D7 – D0
D15 – D8
D23 – D16
D31 – D24
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24