NED
UME-0064-01
XCM40170DLMT2CXP
37
5.4 Digital Processing flow in FPGA
The figure below shows the digital processing flow in the FPGA.
V id e o ( 1 0 b it )
V id e o ( 1 0 b it )
V id e o ( 1 0 b it )
V id e o ( 1 0 b it )
F r o m S e n s o r
F r o m S e n s o r
F r o m S e n s o r
F r o m S e n s o r
-
x
W h it e r e f e r e n c e
W h it e r e f e r e n c e
W h it e r e f e r e n c e
W h it e r e f e r e n c e
m u lt i p l
m u lt i p l
m u lt i p l
m u lt i p l
T e s t P a t t e r n
T e s t P a t t e r n
T e s t P a t t e r n
T e s t P a t t e r n
s e le c t
s e le c t
s e le c t
s e le c t
B la c k r e f e r e n c e
B la c k r e f e r e n c e
B la c k r e f e r e n c e
B la c k r e f e r e n c e
s u b s t r a c t
s u b s t r a c t
s u b s t r a c t
s u b s t r a c t
F P G A P r o c e s s in g b l o c k d i a g r a m
F P G A P r o c e s s in g b l o c k d i a g r a m
F P G A P r o c e s s in g b l o c k d i a g r a m
F P G A P r o c e s s in g b l o c k d i a g r a m
x
V id e o ( 8 o r 1 0 b it )
V id e o ( 8 o r 1 0 b it )
V id e o ( 8 o r 1 0 b it )
V id e o ( 8 o r 1 0 b it )
T o C o a x P r e s s
T o C o a x P r e s s
T o C o a x P r e s s
T o C o a x P r e s s
D r iv e r
D r iv e r
D r iv e r
D r iv e r
D ig it a l G a in
D ig it a l G a in
D ig it a l G a in
D ig it a l G a in
-
D ig it a l O f f s e t
D ig it a l O f f s e t
D ig it a l O f f s e t
D ig it a l O f f s e t
8 o r 1 0 b it
8 o r 1 0 b it
8 o r 1 0 b it
8 o r 1 0 b it
s e le c t
s e le c t
s e le c t
s e le c t
O u t p u t B lo c k
O u t p u t B lo c k
O u t p u t B lo c k
O u t p u t B lo c k
s e le c t
s e le c t
s e le c t
s e le c t
I n T e s t P a t t e r n m o d e , B la c k / W h i t e r e f e r e n c e a n d D i g it a l G a in / O f f s e t w ill b e s k ip e d .
I n T e s t P a t t e r n m o d e , B la c k / W h i t e r e f e r e n c e a n d D i g it a l G a in / O f f s e t w ill b e s k ip e d .
I n T e s t P a t t e r n m o d e , B la c k / W h i t e r e f e r e n c e a n d D i g it a l G a in / O f f s e t w ill b e s k ip e d .
I n T e s t P a t t e r n m o d e , B la c k / W h i t e r e f e r e n c e a n d D i g it a l G a in / O f f s e t w ill b e s k ip e d .
Figure 5-4-1 FPGA Processing Block Diagram
5.5 Startup
When you power on the camera, the camera goes through a series of startup
procedures. During startup, the LED lights orange.
The startup procedure is as follows.
①
The camera initializes the hardware.
②
Reads out the latest camera settings from the flash memory. (User settings if
any or factory default settings)
③
Sets up the camera with the setting values from the flash memory.
When this sequence finishes, the camera is ready to capture and output images.
In order to output images, the Discovery procedure must be done from the frame
grabber board.
