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CHAPTER 15 RESET FUNCTIONS
User’s Manual U14359EJ4V0UM
508
Table 15-2. Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (3/3)
Internal Hardware
Register Name
Initial Value After Reset
DMA addressing control register n (DADCn) (n = 0 to 3)
0000H
DMA byte count register n (DBCn) (n = 0 to 3)
Undefined
DMA channel control register n (DCHCn) (n = 0 to 3)
00H
DMA destination address register nH (DDAnH) (n = 0 to 3)
Undefined
DMA destination address register nL (DDAnL) (n = 0 to 3)
Undefined
DMA disable status register (DDIS)
00H
DMA restart register (DRST)
00H
DMA source address register nH (DSAnH) (n = 0 to 3)
Undefined
DMA source address register nL (DSAnL) (n = 0 to 3)
Undefined
DMA terminal count output control register (DTOC)
01H
DMA functions
DMA trigger source register n (DTFRn) (n = 0 to 3)
00H
Address setup wait control register (ASC)
FFFFH
Bus cycle control register (BCC)
FFFFH
Bus cycle period control register (BCP)
00H
Bus cycle type configuration register n (BCTn) (n = 0, 1)
8888H
Endian configuration register (BEC)
0000H
Bus size configuration register (BSC)
0000H/5555H
Chip area select control register n (CSCn) (n = 0, 1)
2C11H
Bus control
functions
Data wait control register n (DWCn) (n = 0, 1)
7777H
Command register (PRCMD)
Undefined
Power-save control register (PSC)
00H
Clock control register (CKC)
00H
Power-save
control functions
Power-save mode register (PSMR)
00H
Peripheral command register (PHCMD)
Undefined
Peripheral status register (PHS)
00H
System wait control register (VSWC)
77H
Flash programming mode control register (FLPMC)
08H/0CH/00H
On-chip
peripheral
I/O
System control
Lock register (LOCKR)
0
×
H
Caution
“Undefined” in the above table is undefined after power-on-reset, or undefined as a result of
data destruction when RESET
↓↓↓↓
is input and the data write timing has been synchronized.
For other RESET
↓↓↓↓
signals, data is held in the same state it was in before the RESET operation.
Содержание V850E/MA1
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