µ
PD754144, 754244
62
Data Sheet U10040EJ2V1DS
•
µ
PD754244
AC Characteristics (T
A
= –40 to +85
°
C, V
DD
= 1.8 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time
Note 1
t
CY
V
DD
= 1.8 to 2.0 V
1.9
64.0
µ
s
(Minimum instruction execution
V
DD
= 2.0 to 2.7 V
0.95
64.0
µ
s
time = 1 machine cycle)
V
DD
= 2.7 to 6.0 V
0.67
64.0
µ
s
Interrupt input high- and
t
INTH
, t
INTL
INT0
IM02 = 0
Note 2
µ
s
low-level width
IM02 = 1
10
µ
s
KR4 to KR7
10
µ
s
RESET low-level width
t
RSL
10
µ
s
Notes 1.
The CPU clock (
Φ
) cycle time (minimum
instruction execution time) is determined
by the oscillation frequency of the con-
nected resonator (or external clock) and
the processor clock control register (PCC).
The figure on the right shows the cycle
time t
CY
characteristics against the supply
voltage V
DD
when the system clock is used.
2.
2t
CY
or 128/f
X
depending on the setting of
the interrupt mode register (IM0).
0.5
0
Supply voltage V
DD
(V)
1
2
3
4
5
6
1
2
1.9
0.95
0.67
2.7
3
4
5
6
60
64
(During system clock operation)
t
CY
vs. V
DD
Operation guranteed range
1.8
µ
Cycle time t
CY
( s)
*
