NEC mPD789425, Руководство пользователя

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CHAPTER 5 CLOCK GENERATOR
User’s Manual U15075EJ1V0UM00
105
5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following registers.
•
Processor clock control register (PCC)
•
Suboscillation mode register (SCKM)
•
Subclock control register (CSS)
(1) Processor clock control register (PCC)
PCC sets CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 5-2. Format of Processor Clock Control Register
Control of main system clock oscillator operation
MCC 0 0 0 0 0 PCC1 0 PCC
Symbol Address After reset R/W
FFFBH 02H R/W
<7> 6 5 4 3 2 1 0
MCC
0
1
Operation enabled
Operation disabled
CPU clock (f
CPU
) selection
Note
CSS0
0
0
1
1
PCC1
0
1
0
1
f
X
(0.2 s)
f
X
/2 2 (0.8 s)
f
XT
/2 (61 s)
µ
µ
µ
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC) and the CSS0 flag in the subclock control register (CSS) (Refer to 5.3 (3) Subclock
control register (CSS)).
Cautions 1. Bits 0 and 2 to 6 must be set to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU clock.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
4. Minimum instruction execution time: 2f
CPU
•
f
CPU
= 0.2
µ
s: 0.4
µ
s
•
f
CPU
= 0.8
µ
s: 1.6
µ
s
•
f
CPU
= 61
µ
s: 122
µ
s