NEC mPD780852 Series, Предварительное руководство пользователя

Страница: 99 / 315

99
CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U14581EJ3V0UM00
5.6.2 Switching CPU clock
The following figure illustrates how the CPU clock switches.
Figure 5-6. Switching CPU Clock
V
DD
RESET
CPU clock
Slowest
operation Fastest
operation
Wait (15.6 ms: at 8.38-MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the time
during which oscillation stabilizes (2
17
/f
X
) is automatically secured.
After that, the CPU starts instruction execution at the slowest speed of the main system clock (3.81
µ
s: at
8.38-MHz operation).
<2> After a lapse of time long enough for the V
DD
voltage to rise to the level at which the CPU can operate at
its maximum speed, rewrite the contents of the processor clock control register (PCC) to execute the
maximum-speed operation.