NEC MINICUBE2, Руководство пользователя

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CHAPTER 4 HOW TO USE MINICUBE2 WITH 78K0 MICROCONTROLLER
User’s Manual U18371EJ1V0UM
59
Figure 4-7. When Both Debugging and Programming Are Performed
(with OCD1A/OCD1B Communication, X1 Oscillator Is Used) (FLMD1 Pin Is Not Provided)
1
2
3
4
5
6
7
8
9
10
GND
RESET_OUT
V
DD
R.F.U.
R.F.U.
R.F.U.
CLK
Note 2
R.F.U.
GND
_RESET
TxD
V
DD
RxD
11
12
13
14
15
16
R.F.U.
R.F.U.
DATA
FLMD0
RESET_IN Note 4
R.F.U.
FLMD0
8
Port X
OCD1A Note 3
OCD1B Note 3
Target connector Target device
RESET signal
Reset connector
10 k Ω
1 k
Ω
1 k
Ω
10 k Ω
1 to 10 k Ω
3 to 10 k Ω
V
DD
Note 5
1 to 10 k Ω
V
DD
V
DD
V
DD
X1
X2
Clock
circuit
RxD Note 1
TxD
Note 1
Note 4
V
DD
3 to
10 k
Ω
1
2
3
4
5
6
7
8
9
10
GND
RESET_OUT
V
DD
R.F.U.
R.F.U.
R.F.U.
CLK
Note 2
R.F.U.
GND
_RESET
TxD
V
DD
RxD
11
12
13
14
15
16
R.F.U.
R.F.U.
DATA
FLMD0
RESET_IN Note 4
R.F.U.
FLMD0
8
Port X
OCD1A Note 3
OCD1B Note 3
Target connector Target device
RESET signal
Reset connector
10 k Ω
1 k
Ω
1 k
Ω
10 k Ω
1 to 10 k Ω
3 to 10 k Ω
V
DD
Note 5
1 to 10 k Ω
V
DD
V
DD
V
DD
X1
X2
Clock
circuit
RxD Note 1
TxD
Note 1
Note 4
V
DD
3 to
10 k
Ω
Notes 1. Connect TxD (transmit side) of the target device to RxD (receive side) of the target connector, and TxD
(transmit side) of the target connector to RxD (receive side) of the target device.
2. During debugging, the clock mounted on the 78K0-OCD board can be supplied. If no clock is mounted, a
clock of 4, 8, or 16 MHz can be supplied (neither of them is used for the CPU operating clock). During
flash programming, only a clock of 4, 8, or 16 MHz can be supplied.
3. OCD1A (OCD1B) may be a different name, such as P31, depending on the device used. Check the pin
name with the user
'
s manual for the target device. Since this pin is dedicated to debugging during
debugging, port settings made by the user program are ignored. If this pin is assigned to an input port,
the pin must be connected as shown in this figure, because it is open when MINICUBE2 is not connected.
4. This connection is designed assuming that the RESET signal is output from the N-ch open-drain buffer
(output resistance: 100
Ω
or less). For details, refer to 4.1.3 Connection of reset pin .
5. The circuit enclosed by a dashed line is designed for flash self programming, which controls the FLMD0 pin
via ports. Use the port for inputting or outputting the high level. When flash self programming is not
performed, a pull-down resistance for the FLMD0 pin can be within 1 to 10 k
Ω
.