Nautel XR6, Руководство по устранению неисправностей, Страница: 80 / 291

XR6/XR3 Troubleshooting Manual Detailed Circuit Descriptions
Page 2-12 Issue 3.0 2009-07-15
During normal operation, C58 will charge through R67 towards 15 V when the PDM1 output is 15 V
(during its 'on time') and CR3 is reversed biased. It will instantly discharge to ground potential,
through CR3, when the PDM1 output switches to 0 V (during its 'off time'). The repetition rate of
the PDM1 on/off periods ensures the charge on C58 will not exceed 7.3 V, provided each PDM1
cycle contains an 'off time'. If a PDM failure occurs that produces a continuous 'on time', C58 will
charge more positively than 7.3 V. U12A's output will switch to a current-sink-to-ground and toggle
the shutback latch circuit to its 'set' state.
Shutback latch
The shutback latch circuit inhibits the 'on time' of the PDM outputs and, in turn, the RF output of
the transmitter whenever a transmitter originated
Inhibit PDM (J1-16) command is applied. This
circuit provides additional protection to the transmitter's RF power stages when faults are detected or
actions are initiated that may cause RF stress current thresholds to be exceeded. Its function is to de-
energize K1 and disconnect the
PDM 1/PDM 2 outputs from the transmitter circuits when the PDM
fault detector output is a current-sink-to-ground (logic low). It also inhibits the PDM generators
when relay K1 is de-energized or when a logic true
inhibit PDM command is applied to J1-16.
U9A/U9B form a bistable flip/flop. The flip-flop's output, at U9-3, will be 15 V (logic high) when in
its 'reset' state, and a current-sink-to-ground (logic low) when in its 'set' state.
Normally the inhibit PDM input and the output of the PDM fault detector circuit, which are the flip-
flop's controlling inputs, are open collector. 5 V (logic high) are applied to U9-1 and U9 5 through
their pull-up resistors and the flip-flop is latched in its 'reset' state. Relay K1 is held energized and the
PDM outputs are applied to the transmitter circuits.
If a PDM fault is sensed, the PDM fault detector circuit applies a current-sink-to-ground (logic low)
to U9-5 and causes the flip-flop to switch to and latch in its 'set' state. Relay K1 de-energizes and
disconnects both PDM outputs from the transmitter circuits. The PDM latch output (J1-11) is
activated (5 V). This condition is maintained until the flip-flop is reset by the removal of the logic low
from U9-5 (no PDM fault) and the application of logic low to U9-1 (a logic true current-sink-to-
ground
reset PDM command is applied to J1-1).
PDM inhibit
The PDM inhibit circuit consists of U9D, Q2, Q3, and their associated circuits. Its function is to
instantly clamp the output of both PDM generators to ground (zero carrier level) whenever a logic
true (current-sink-to-ground)
inhibit PDM input is applied to J1-16, or when the PDM fault detector
circuit senses a PDM fault and the shutback latch circuit's flip-flop is latched in its 'set' state. When
neither of these conditions are true, the PDM inhibit circuit has no influence.