Nautel XR6, Руководство по устранению неисправностей, Страница: 79 / 291

XR6/XR3 Troubleshooting Manual Detailed Circuit Descriptions
Issue 3.0 2009-07-15 Page 2-11
Figure 2.1: Timing Diagram for PDM Differential Amplifier
PDM2 generator
The PDM2 generator consists of U3C, U11B, Q6, Q7, and their associated components. It operates
similar to the PDM1 generator except U3C inverts the compensated
carrier ref + audio input and
applies it to differential comparator U11B's inverting input. The result is a PDM2 'on period' when
the compensated
carrier ref + audio is less positive than the triangular waveform and produces a
minimum 'on time' at the positive peaks of the triangular waveform. The on/off ratio of the PDM1
and PDM2 outputs are the same, but the zero power reference change for the PDM2 output is offset,
relative to the PDM1 output, by one half of the PDM repetition rate.
PDM fault detector
The PDM fault detector circuit contains two identical voltage controlled switches (one for each PDM
output) that control the 'set/'reset' status of the shutback latch circuit and, in turn, controls the on/
off status of relay K1. For explanation purposes, only the PDM1 fault detector is described.
The PDM1 fault detector circuit consists of U12A and its associated components. R67/C58 form an
integrator with a long time constant, relative to the PDM frequency. C58's charge voltage is applied to
U12A's inverting input and compared to the 7.3 V reference voltage applied to its non-inverting input
from voltage divider R70/R71/ R72. U12A's output is an open collector and has no influence when
C58's charge voltage is less positive than the reference voltage. U12A's output will switch to a
current-sink-to-ground when C58's charge voltage goes more positive than the reference voltage.
Inverted Carrier
Ramp
PDM 2
Reference Level
PDM 1
Ramp
Carrier Reference
Level