Nations Technologies Inc.
Tel
:
+86-755-86309900
:
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
521
/
631
be achieved.
In slave mode, the NSS pin is low, and when the first clock edge arrives, the transmission process begins. In order to
avoid accidental data transmission, software must write data to the transmit buffer before data transmission (it is
recommended to enable the SPI module before the host sends the clock).
In some configurations, when the last data is sent, the BUSY flag (SPI_STS.BUSY) can be used to wait for the end
of the data sending.
Continuous and discontinuous transmission.
When sending data in master mode, if the software is fast enough to detect each TE (SPI_STS.TE) rising edge (or
TE interrupt), and the data is written to the SPI_DAT register immediately before the end of the ongoing transmission.
At this time, the SPI clock remains continuous between the transmission of data items, and the SPI_STS.BUSY bit
will not be cleared, continuous communication can be achieved.
If the software is not fast enough, it will result in discontinuous communication; in this case, the SPI_STS.BUSY bit
is cleared between the transmission of each data items (see Figure 24-10 below).
In master receive-only mode (SPI_CTRL1.RONLY = 1), communication is always continuous and the BUSY flag
(SPI_STS.BUSY) is always high.
In slave mode, the continuity of communication is determined by the SPI master device. However, even if the
communication is continuous, the BUSY flag (SPI_STS.BUSY) will be low for at least one SPI clock cycle between
each data item (see Figure 24-9).
Figure 24-10 Schematic diagram of TE/BUSY change when BIDIRMODE = 0 and RONLY = 0 are transmitted
discontinuously
Status flag
The SPI_STS register has 3 flag bits to monitor the status of the SPI:
Send buffer empty flag bit (TE)
When the send buffer is empty, the TE flag (SPI_STS.TE) is set to 1, which means that new data can be written into
the SPI_DAT register. When the send buffer is not empty, the hardware will clear this flag to 0.
`
DATA1=0x11
SCK
MOSI
(
out
)
TE flag
Tx buffer
(
write to SPI_DAT
)
Configure
:
CLKPOL=1.CLKPHA=1
0x11
0x22
0x33
Wait until TE=1,write 0x33 into SPI_DAT
Write 0x11 into SPI_DAT
Wait until TE=1,write 0x22 into SPI_DAT
b0
b2
b1
b3
b4
b6
b5
b7
b0
b2
b1
b3
b4
b6
b5
b7
b0
b2
b1
b3
b4
b6
b5
b7
DATA2=0x22
DATA3=0x33
BUSY flag
Wait TX=1
Wait BUSY=0