National Semiconductor TPS65132S, Руководство пользователя

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5
4
1
2
3
6
J1
4
1
2
3
J5
5
4
1
2
3
6
J2
5
4
1
2
3
6
J3
5
4
1
2
3
6
J6
1 2
3 4
5 6
7 8
9 10
J4
4.7µF
C4
GND
GND
GND
GND
GND
GND
GND
GND
GND
4.7µF
C1
GND
OUTP
OUTN
REG
VIN
CFLY1
SW
VIN
2.5V to 5.5V
S+
GND
ON
EN
OFF
ON
SYNC
OFF
VPOS
S+
GND
VNEG
S-
GND
REG
GND
GND
VIN
VIN
TP4
4 V to 6 V
-6 V to -4 V
TP2
TP3
TP1
1
2
3
JP2
1
2
3
JP1
AGND
D2
CFLY1
C3
CFLY2
A3
SYNC
A1
EN
B1
OUTP
E3
OUTN
A2
PGND
B3
PGND
E1
REG
D3
REG
E2
SCL
B2
SDA
C2
SW
D1
VIN
C1
U1
TPS65132SYFF CFLY2
4.7µF
C2
10µF
C3
10µF
C5
2.2µH
L1
Copyright © 2016, Texas Instruments Incorporated
Schematic
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4 SLVUAY0 – November 2016
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Copyright © 2016, Texas Instruments Incorporated
TPS65132S Evaluation Module
3 Schematic
Figure 1 is for reference only; see the bill of materials in Section 8 for specific values.
Figure 1. Schematic