National Semiconductor SERDES05-40USB, Руководство пользователя

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SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 7 of 37
SERDES Serializer Board Description:
The 50-pin IDC connector J1 accepts 24 bits of LVCMOS RGB data along with the
clock input.
The SERDES Serializer board is powered externally from the J4 (VDD) and J5 (VSS)
connectors shown below. For the Serializer to be operational, the Power Down (S1-
TPWDNB) and Data Enable (S1-DEN) switches on S1 must be set HIGH. The board is
factory configured (with series capacitors on the FPD-LINKII outputs) in AC coupled
mode: S1- RESVRDA, RESVRDB, and VODSEL must be set LOW. Rising or falling
edge reference clock is also selected on S1-TRFB: HIGH (rising) or LOW (falling).
The USB connector P2 (USB-A side) on the bottom side of the board provides the
interface connection to the FPD-LINKII signals to the De-serializer board. Note: P1
(mini USB) on the top side is un-stuffed and not to be used with the cable provided in
the kit.
Note:
VDD and VSS
MUST
be applied externally
from here.
c
P2 (BACKSIDE)
f
J4, J5
c
FPD-LINK II OUTPUTS
d
LVCMOS INPUTS
e
FUNCTION CONTROLS
f
POWER SUPPLY
g
49.9
Ω
INPUT TERMINATION
(For 50
Ω
signal sources,
remove otherwise if populated.)
e
JP3
J1
d
S1
e
g
g
g
g
c
P1 (TOPSIDE)
( UNSTUFFED)
Note:
Connect cable
(USB A side)
to P2 on
BACKSIDE .