SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 11 of 37
Tx LVCMOS and FPD-LINK
II
Pinout by IDC Connector
The following three tables illustrate how the Tx inputs are mapped to the IDC connector
J1, the FPD-LINKII outputs on the USB-A connector P2, and the mini USB P1 (not
installed) pinouts. Note – labels are also printed on the demo boards for both the
lvcmos input and FPD-LINKII outputs.
J1
P2
P1
LVCMOS INPUT
(bottom side)
(topside)
pin
no. name
name
pin
no.
FPD-LINK
II
OUTPUT
(not mounted)
1
GND
DIN0
2
pin no.
name
FPD-LINK
II
OUTPUT
3
GND
DIN1
4
1
JP1
pin no.
name
5
GND
DIN2
6
2
DOUT+
5 JP2
7
GND
DIN3
8
3
DOUT-
4 NC
9
GND
DIN4
10
4
JP2
3
DOUT-
11
GND
DIN5
12
2
DOUT+
13
GND
DIN6
14
1
JP1
15
GND
DIN7
16
17
GND
DIN8
18
19
GND
DIN9
20
21
GND
DIN10
22
23
GND
DIN11
24
25
GND
DIN12
26
27
GND
DIN13
28
29
GND
DIN14
30
31
GND
DIN15
32
33
GND
DIN16
34
35
GND
DIN17
36
37
GND
DIN18
38
39
GND
DIN19
40
41
GND
DIN20
42
43
GND
DIN21
44
45
GND
DIN22
46
47
GND
DIN23
48
49
GND
TCLK
50
