L M K 0 3 0 0 2 C
E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
16
The PLL tab shows a conventional PLL diagram along with the VCO Divider. It is important to
realize that the total effective N value is PLL N Counter * VCO Divider. This means that the
“channel spacing” is the Phase Detector Frequency * VCO Divider. Depending on the
situation, this may require the R Counter multiplied up by the value of the VCO Divider to achieve
desired VCO output frequencies.
Example: If the desired VCO output frequency was 1648 MHz, R would need to be increased to
2 before 1648 MHz could be programmed because of the VCO Divider of 2 would only allow
programming of 1600, 1632, 1664, etc. with a 16 MHz phase detector frequency – because
changing the N counter from 51 to 52 changes to total N by two, 102 to 104!
