National Semiconductor LM628, Руководство по программированию

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I. Program Modules
(Continued)
In the case of the example module, the second byte of the
RSTI data word, 00 hex, resets
all interrupt flag bits. See
Table 1 .
DAC Port Size
During both hardware and software resets, the DAC output
port defaults to 8-bit mode. If an LM628 control loop utilizes
a 12-bit DAC, command PORT12 should be issued immedi-
ately following the hardware reset block and all subsequent
resets. Failure to issue command PORT12 will result in
erratic, unpredictable motor behavior.
If the control loop utilizes an 8-bit DAC, command PORT12
must not be executed; this too will result in erratic, unpre-
dictable motor behavior.
An LM629 will ignore command PORT8 (as it provides an
8-bit sign/magnitude PWM output). Command PORT12
should not be issued in LM629-based systems.
Software Reset Considerations
After the initial hardware reset, resets can be accomplished
with either a hardware reset or command RESET (software
reset). Software and hardware resets execute the same
tasks (Note 6) and require the same execution time, 1.5 ms
maximum. During software reset execution, the LM628 will
ignore any commands or attempts to transfer data.
The hardware reset module includes an LM628 functionality
test. This test is
not required after a software reset.
Table 2 details an initialization module that uses a software
reset.
Note 6: In the case of a software reset, the position error threshold remains
at its pre-reset value.
TABLE 2. Initialization Module (with Software Reset)
Port Bytes Command Comments
c 00 RESET See Initialization Module text.
wait The maximum time to complete RESET tasks is 1.5 ms.
c 06 PORT12 The RESET default size of the DAC port is eight bits. This command initializes the DAC
port for a 12-bit DAC. It should not be issued in a system with an 8-bit DAC.
Busy-bit Check Module
c 1D RSTI This command resets only the interrupts indicated by zeros in bits one through six of
the next data word. It also resets bit fifteen of the Signals Register and (pin 17) the host
interrupt output pin.
Busy-bit Check Module
d xx HB Don’t care
d 00 LB Zeros in bits one through six indicate all interrupts will be reset.
Busy-bit Check Module
Comments
Figure 7 illustrates, in simplified block diagram form, the
LM628. The profile generator provides the control loop input,
desired shaft position. The quadrature decoder provides the
control loop feedback signal, actual shaft position. At the first
summing junction, actual position is subtracted from desired
position to generate the control loop error signal, position
error. This error signal is filtered by the PID filter to provide
the motor drive signal.
After executing the example initialization module, the follow-
ing observations are made. With the integration limit term (i
L
)
and the filter gain coefficients (k
p
, k
i
, and k
d
) initialized to
zero, the filter gain is zero. Moreover, after a reset, desired
shaft position tracks actual shaft position. Under these con-
ditions, the motor drive signal is zero. The control system
can not affect shaft position. The shaft should be stationary
and “free wheeling”. If there is significant drive amplifier
offset, the shaft may rotate slowly, but with minimal torque
capability.
Note: Regardless of the free wheeling state of the shaft, the LM628 continu-
ously tracks shaft absolute position.
high byte
01086007
low byte
01086008
FIGURE 6. Interrupt Mask/Reset Bit Allocations
AN-693
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