National Semiconductor LM628, Руководство по программированию

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I. Program Modules
(Continued)
Reset Interrupts
TABLE 1. Initialization Module (with Hardware Reset)
Port Bytes Command Comments
(Note 5) hardware
reset
Strobe RST, pin 27, logic low for eight clock periods minimum.
wait The maximum time to complete hardware reset tasks is 1.5 ms. During this reset
execution time, the LM628 will ignore any commands or attempts to transfer data.
c
(Note 2)
xx
(Note 3)
RDSTAT This command reads the status byte. It is directly supported by LM628 hardware and
can be executed at any time by pulling CS, PS, and RD logic low. Status information
remains valid as long as RD is logic low.
decision If the status byte is C4 hex or 84 hex, continue. Otherwise loop back to hardware reset.
c 1D RSTI This command resets only the interrupts indicated by zeros in bits one through six of
the next data word. It also resets bit fifteen of the Signals Register and the host
interrupt output pin (pin 17).
Busy-bit Check Module
d xx HB
(Note 4)
don’t care
d 00 LB Zeros in bits one through six indicate all interrupts will be reset.
Busy-bit Check Module
c xx RDSTAT This command reads the status byte.
decision If the status byte is C0 hex or 80 hex, continue. Otherwise loop back to hardware reset.
c 06 PORT12 The reset default size of the DAC port is eight bits. This command initializes the DAC
port for a 12-bit DAC. It should not be issued in systems with an 8-bit DAC.
Busy-bit Check Module
Note 2: The 8-bit host I/O port is a dual-mode port; it operates in command or data mode. The logic level at PS (pin 16) selects the mode. Port c represents the
LM628 command port-commands are written to the command port and the Status Byte is read from the command port. A logic level of “0” at PS selects the command
port. Port d represents the LM628 data port — data is both written to and read from the data port. A logic level of “1” at PS selects the data port.
Note 3: x - don’t care
Note 4: HB - high byte, LB - low byte
Note 5: All values represented in hex.
An RSTI command sequence allows the user to reset the
interrupt flag bits, bits one through six of the status byte. See
Figure 5 . It contains an RSTI command and one data word.
The RSTI command initiates resetting the interrupt flag bits.
Command RSTI also resets the host interrupt output pin (pin
17).
Immediately following the RSTI command, a single data
word is written. The first byte is not used. Logical zeros in
bits one through six of the second byte reset the correspond-
ing interrupts. See
Figure 6 . Any combination of the interrupt
flag bits can be reset within a single RSTI command se-
quence. This feature allows interrupts to be serviced accord-
ing to a user-programmed priority.
01086006
FIGURE 5. Status Byte Bit Allocation
AN-693
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