National Semiconductor LM628, Руководство по программированию

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I. Program Modules
(Continued)
BUSY-BIT CHECK MODULE
The first module required for successful programming of the
LM628 is a busy-bit check module.
The busy-bit, bit zero of the status byte, is set immediately
after the host writes a command byte, or reads or writes the
second byte of a data word. See
Figure 5 . While the busy-bit
is set, the LM628 will ignore any commands or attempts to
transfer data.
A busy-bit check module that polls the Status Byte and waits
until the busy-bit is reset will ensure successful host/LM628
communications.
It must be inserted after a command
write, or a read or write of the second byte of a data
word.
Figure 3 represents such a busy-bit check module.
This module will be used throughout subsequent modules
and programs.
Reading the Status Byte is accomplished by executing a
RDSTAT command. RDSTAT is directly supported by LM628
hardware and is executed by pulling CS, PS, and RD logic
low.
INITIALIZATION MODULE
In general, an initialization module contains a reset com-
mand and other initialization, interrupt control, and data re-
porting commands.
The example initialization module, detailed in Table 1 , con-
tains a hardware reset block and a PORT 12 command.
Hardware Reset Block
Immediately following power-up, a hardware reset must be
executed. Hardware reset is initiated by strobing RST (pin
27) logic low for
a minimum of eight LM628 clock periods.
The reset routine begins after RST is returned to logic high.
During the reset execution time,
1.5 ms maximum, the
LM628 will ignore any commands or attempts to transfer
data.
A hardware reset forces the LM628 into the state described
in what follows.
1. The derivative sampling coefficient, d
S
, is set to one, and
all other filter coefficients and filter coefficient input buff-
ers are set to zero. With d
S
set to one, the derivative
sampling interval is set to 2048/f
CLK
.
2. All trajectory parameters and trajectory parameters input
buffers are set to zero.
3. The current absolute position of the shaft is set to zero
(“home”).
4. The breakpoint interrupt is masked (disabled), and the
remaining five interrupts are unmasked (enabled).
5. The position error threshold is set to its maximum value,
7FFF hex.
6. The DAC output port is set for an 8-bit DAC interface.
Figure 4 illustrates a hardware reset block that includes an
LM628 functionality test. This test should be completed im-
mediately following all hardware resets.
01086003
FIGURE 3. Busy-bit Check Module
01086005
FIGURE 4. Hardware Reset Block
AN-693
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