P1
U8
VR1
VR2
S1
L1
L5
U6
U7
RP3
R37
HDR2
HDR1
RP2
RP1
TP8
+12V
TP7
+5V
TP6
-12V
U2
U1
U3
JP3
JP2
TP13 TP12
T1
J2
J1
JP1
AGND
TP11
VREF
U4
ADC14071
TP4
ADC CLK
JP4
CLK SEL
TP2
OR
TP9
PLD CLK
D3
Over
Range
D5
CLK
AGND
DGND
TP5
OE
NATIONAL SEMICONDUCTOR
DATA CONVERSION SYSTEMS GROUP
Y1
U9
JP6
MADE IN USA
D4
Under
Range
D6
COMMO
JP5
DGND
TP10
EXT CLK
ADC14071 Evaluation Board
L4
L3
L2
DGND
TP3
PD
Signal
Input
J1
Ext. Clock
Input
J2
Reference
Adjust
VR2
Power
Connector
P2
S1
Reset
Button
Input
Select
JP1
V
REF
Test
Point
Clock Source
Select
JP4
Balance
VR1
Clock
Termination
JP5
Parallel Port
Connector
P1
Jumper
default
positions
JP2 &
JP3
JP4 &
JP6
JP1
DRV
Select
JP1 & JP2
Breadboard
Area
Figure 1. Component and Test Point Locations
3.3 Board Outputs.
U6. During data acquisition, the RAM address is incremented
by U6. After the data is gathered and loaded into RAM, it is
read from RAM by U6 and sent over the computer-board
cable. The number of words sent is determined by the
instructions from the host computer.
Uploading of data to a PC running WaveVision is
accomplished through Parallel Port connector P1.
The buffered digital data from the ADC14071 output, as well
as a clock signal for this data, is available at 20 pin headers
HDR1 and HDR2. These connectors have all the even
numbered pins grounded and are suitable for connecting
ribbon cables to the board.
3.6 Computer Interface.
The board communicates with a host computer through a
parallel interface. The data path is through the DB-25
connector P1, located at the right side of the board. The
parallel interface uses a PC parallel port that must support
either EPP mode or ECP mode.
LEDs provide visual indication of the condition of the board.
Red LED D5, when lit, indicates that a clock signal is present
at the clock input to the ADC14071. Yellow LED D6 indicates
the status of board-PC communications. The board is
sending data to the computer when this LED is on.
3.7 Power requirements.
Power is supplied to this board through power connector P2
at the top right of the board. The board requires 1 Amp at
+12V to +15V and 10mA at -12V to -15V. The board is
protected from accidental polarity reversal with series diodes
in both the positive and negative supply lines.
Two LEDs are provided as an indicator that the input to the
ADC is beyond the ADC's range. Yellow LED D3 indicates
when the input is beyond the maximum positive range, while
Greed LED D4 indicates when the input is beyond the lowest
negative value allowable to avoid signal clipping. Input signal
levels that just prevent these LEDs from coming on will
provide maximum SNR performance.
4.0 Installing and using the ADC14071 Evaluation
Board and WaveVision Software
3.4 Board Control.
The evaluation board requires power as described in
paragraph 3.7. No input signals for evaluation are generated
on the board. An appropriate signal generator (such as
HP8662A) with a 50- to 75-Ohm source impedance should be
used to evaluate the performance of the ADC14071. The
generator output should be filtered by a bandpass filter when
evaluating sinusoidal signals to eliminate unwanted
frequencies (harmonics and noise) from the generator. This
will provide dynamic readings that are a more accurate
assessment of the converter performance than you would
obtain without the filter. This is because even the best signal
PLD U6 is a state machine that performs the control functions
of the board. It also contains registers and logic used to move
data. The functions of this device are:
•
Write acquired data to RAM.
•
Accept and interpret commands from the computer.
•
Divide the clock input frequency per command.
•
Upload data in RAM to PC via parallel port.
3.5 Data Memory.
The data memory consists of a single 64k x 16 RAM chip, U7.
Data is written to RAM from the ADC14071 by way of PLD
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