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4.0 Functional Description
Table 1
describes the function of the various
jumpers on the ADC122S655 evaluation board.
The evaluation board schematic is shown in
Figure 10
.
Jumper
Pins 1 & 2
Pins 2 & 3
JP8
Select V
A
as V
REF
2.5V reg.
as V
REF
JP11
5.0V
external supply
5.0V from
J6 (WV4S)
JP12
Select on-board
clock OSC Y2
Select external
clock from TP15
JP14
Enable OSC (not required)
Table 1: Jumper Configurations
4.1 Analog Input Signal
The input signal to be digitized can be a
differential voltage or a single-ended signal. A
differential signal can have a maximum value of
+/-VREF and is applied across pins 1 & 3 of J3 for
channel A and pins 4 & 6 of J3 for channel B.
Pins 2 and 5 are grounds. A single-ended signal
can have a maximum value of 2V
REF
and a
minimum value of 0V. The signal may be applied
to either the non-inverting or inverting input. The
opposing input pin must be driven by a maximum
voltage of V
REF
where V
REF
< V
A
/ 2.
R31 and R38 are terminating resistors for the
input source. Since all sources do not have the
same output impedance, those resistors are not
populated. However, those resistors should be
added by the user with the appropriate value that
matches the source.
When using an AC coupled input signal, DC
biasing is required. DC biasing is available for
inputs applied to J3 but is currently not populated
on the board. Add 4.99 k
Ω
resistors to R27, R28,
R29, R33 to achieve a V
A
/2 DC bias on channel A
and add 4.99k
Ω
resistors to R25, R26, R35, R37
to achieve a V
A
/2 DC bias on channel B. Proper
DC biasing will allow each input to swing the full
range (-V
REF
/2 to +V
REF
/2) where V
REF
< V
A
.
Dynamic input signals should be applied through
a bandpass filter to eliminate the noise and
harmonics commonly associated with signal
sources. To accurately evaluate the performance
of the ADC122S655, the source must be better
than -90dBc THD.
4.2 ADC Reference Circuitry
This evaluation board includes the option of
selecting a fixed 2.5V reference voltage, V
A
, or an
external voltage as the reference voltage. Select
the 2.5V reference as V
REF
by shorting pins 2 & 3
of JP8 or select V
A
as V
REF
by shorting pins 1 & 2
of JP8. If it is desirable to provide an external
reference voltage, the jumper must be removed
from JP8 and TP11 may be driven directly. The
recommended range for V
REF
is 1.0V to V
A
.
4.3 SPI Interface
4.3.1 ADC Clock (SCLK)
The clock frequency can range from 6.4MHz to
16MHz. The 16MHz crystal-based oscillator
provided on the evaluation board is selected by
shorting pins 1 & 2 of JP12. It is best to remove
any external signal generator when using this
oscillator to reduce any unnecessary noise.
This board will also accept a clock signal from an
external source by connecting that source to TP15
(CLK_IN) and shorting pins 2 & 3 of JP12. The
input at TP15 is terminated by R45 (value 51
Ω
).
To reduce any unnecessary noise, it is best to
remove the oscillator at Y2 when using an
external clock source.
Regardless of the clock source selected by JP12,
the clock signal is designed to be routed off the
ADC122S655 evaluation board to the WV4 board.
This assumes computer mode operation of the
evaluation board. For applications utilizing the
evaluation board in manual mode, the clock is
applied directly at J6 or VIA6.
4.3.2 Digital Data Output (DOUT)
The ADC122S655 takes two input signals
(channel A and channel B) and outputs to a single
data output line (DOUT). The output format is 2’s
complement with channel A’s conversion result
followed by channel B’s conversion result. The
DOUT can be monitored at VIA7 or pin 5 of J6. In
computer mode, the DOUT is by the use of the
WV4 board and WaveVision 4 software. See the
Evaluation Board schematic (
Figure 10)
and
ADC122S655 datasheet for further details.
4.3.3 Chip Select Bar (CSB)
The CSB pin may be monitored at VIA5 or pin 1 of
J6. In computer mode, the CSB is provided by the
WV4 board. In manual mode, the CSB should be
driven directly at J6. The signal level for CSB
needs to be CMOS compatible. See the
ADC122S655 datasheet for logic threshold limits.
