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4
2.0 Board Assembly
The ADC122S655EB evaluation board comes
fully assembled and ready for use. The provided
shorting jumpers are in their recommended
locations and suit the needs of most users. The
evaluation board also includes a crystal oscillator
(Y2). Refer to the Bill of Materials for a
description of components, to
Figure 1
for major
component placement, and to
Figure 10
for the
evaluation board schematic.
While the board has been populated in a manner
that is most advantageous for typical usage, the
board can be customized by adding components
to meet the user’s specific needs. The board
comes ready to use with a DC coupled input
signal (
Figure 2
). However, by adding capacitors
C21, C22, C25, C26 (value 1µF), adding DC bias
resistors R25, R26, R27, R28, R29, R33, R35,
R37 (value 4.99k
Ω
), and removing R30, R34,
R36, R40 (value 20
Ω
), the board can be used with
an AC coupled input signal (
Figure 3
).
A-VIN
R30 20
R34
20
R36 20
R40
20
A-VBIAS
R35 NS
C21
NS
R33 NS
B-VIN
C25
NS
C26
NS
R38
NS
VA_M
R29 NS
R37 NS
C22
NS
R26
NS
R28
NS
R27
NS
R25
NS
R31
NS
B-VBIAS
J3
HEADER 6
1
2
3
4
5
6
Figure 2: DC Coupled Input Configuration
A-VIN
R30 NS
R34
NS
R36 NS
R40
NS
A-VBIAS
R35 4.99K
C21
1UF
R33 4.99K
B-VIN
C25
1UF
C26
1UF
R38
NS
VA_M
R29 4.99K
R37 4.99K
C22
1UF
R26
4.99K
R28
4.99K
R27
4.99K
R25
4.99K
R31
NS
B-VBIAS
J3
HEADER 6
1
2
3
4
5
6
Figure 3: AC Coupled Input Configuration
The board was tested with several different
capacitor configurations, and the best
performance was found to occur when capacitors
C37, C38, C39, C40 were not populated and only
differential capacitors C31 and C32 were left in
place. If your analog input signal has a great deal
of common-mode noise, the user can populate
C37, C38, C39, C40 with 470pF capacitors.
3.0 Quick Start
The ADC122S655EB evaluation board may be
used in the Stand-Alone mode to capture data
with a logic analyzer or third party equipment, or it
may be used in the Computer Mode with a
WaveVision 4 Data Capture Board, referenced
throughout the remainder of this document as
WV4. In both cases, the data may be analyzed
with the WaveVision 4 software.
3.1 Stand Alone Mode
Refer to
Figure 1
for locations of test points and
major components.
1. Remove the jumper from
JP12
and the
oscillator
Y2
from its socket. The SPI interface
signals (CSB and SCLK) may be driven
directly at
J6
or with wires soldered to VIA5
and VIA6 (step 7). DOUT may also be
monitored at J6 or with a wire at VIA7.
Frequently, a Logic Analyzer with a built-in
pattern generator is used to drive CSB and
SCLK while monitoring the data output. It is
necessary to remove Y2 because the
presence of a second clock source could add
noise to the conversion process.
2. Connect a clean analog (not switching) +5.0V
power source with a 300mA current limit to
the external power connector
TP12
. Ground
TP13
.
3. Place a shorting jumper across
pins 1 & 2 of
JP11
and turn on the power supply.
4. To analyze the performance of channel A,
connect a differential signal across
pins 1 & 3
of J3
(pin 2 is ground). Please note the
evaluation board is assembled for a DC-
coupled input source. To analyze channel B,
connect your signal across
pins 4 & 6 of J3
(pin 5 is ground). If the source has a 50 ohm
output impedance, install a 51 ohm resistor at
R31 or R38, depending on which channel you
are using (match the source impedance with
resistors R31 or R38). To accurately evaluate
the performance of the ADC122S655, the
source must be better than 90dB THD.
5. Select the 2.5V voltage reference as V
REF
by
placing a shorting jumper across
pins 2 & 3
of JP8
.
6. If it is desirable to provide an external
reference voltage, the jumper must be
removed from JP8 and TP11 (VREF) may be
driven directly. Refer to the datasheet for
acceptable common mode voltage ranges for
specific reference voltages.
