National Semiconductor ADC08200, Инструкция по эксплуатации, Страница: 13 / 16

APPENDIX
Summary Tables of Test Points and Connectors
Test Points on the ADC08200 Evaluation Board
TP 1 Signal Input test point
TP 2 ADC Top Reference Voltage, VRT
TP 3 ADC Bottom Reference Voltage, VRB
TP 4 Ground
TP 5 Ground
TP 6 Ground
TP 7 +3V test point (Groundedd on initial board version)
P1 Connector - Power Supply Connections
J4-1 +5V Positive Power Supply
J4-2 GND Power Supply Ground
J4-3 +5V Logic and Digital Interface Board Supply
J4-4 -5.2 Negative Power Supply
JP1 Jumper - ADC Clock
Connect 1-2 Divide Clock Oscillator (Y1) frequency by 2
Connect 2-3 Use Clock Oscillator (Y1) frequency without dividing it (Default)
JP2 Jumper - Memory
Connect 1-2 Use one FIFO chip
Connect 2-3 Use both FIFO chips (Default hard-wired position)
JP3 thru JP6 - Not Used
JP7 Jumper - Divide Enable
Connect 1-2 Use both FIFO chips - divide FIFO read signal frequency by 2 (Default hard-wired position)
Connect 2-3 Use one FIFO chip - do not divide FIFO read signal
JP8 Jumper - Number of Memory Chips
Connect 1-2 One Memory Chip
Connect 2-3 Two Memory Chips (Default hard-wired position)
JP9 Jumper - Power Down
No Jumper ADC080200 in active state
Jumper Present ADC080200 in Power Down mode
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