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Figure 2a. ADC 08200 Evaluation Board Schematic

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

C17
1uF

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

1

0

D

1

1

D

1

2

D

1

3

D

1

4

L2

CHOKE

5

6

7

4

2

3

1

8

+

-

+5V

-5.2V

U5

LM358N

+3VCC

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

V

A

AGND

V

RT

V

A

AGND

V

I N

VIN GND

AGND

V

RM

V

RB

AGND

V

A

CLK

PD

D0

D1

D2

D3

DR VD

DR GND

D4

D5

D6

D7

U3

ADC08200

+3VCC

+3VCC

R35

8 X 47

+3VCC

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

ADCCLK

U8

CY7C4281

or

IDT72251L10J

+5V

D7

D6

D5

RD1

RD0

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

R

D

7

R

D

6

R

D

5

R

D

4

R

D

3

R

D

2

D

4

D

3

D

2

D

1

D

0

U10

CY7C4281 

or

IDT72251L10J

D7

D6

D5

RD1

RD0

J4

Power

Connector

+5V

GND

+5V

-5.2V

1

2

3

4

U7

LM317T

4

2

5

1

IN

ON/OFF

OUT

ADJ

3

D1

1N4001

D4

1N4001

D2

1N4001

L4

CHOKE

L3

CHOKE

C26

33uF

6.3V

+3VCC

+5VA

+5V

-5.2V

C31

47uF

6.3V

C21

100uF

6.3V

C19

33uF

6.3V

R47

240,

1%

R46

330,

1%

U9B

74AC74SC

7       1

2

3

5

6

D

CLK

Q

_

Q

PR

CL

GND

Vcc

14        4

+5V

3

2

1

JP7

DIVEN

7     13

12

11

9

8

D

CLK

Q

_

Q

PR

CL

GND

Vcc

14     10

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

+5V

U9A

74AC74SC

+5V

+5VA

-5.2V

R48

8 x 1k

R49

8 x 47

R40
220

R45

47

RV1

1k

VRT

RV2

1k

VRB

-

+

+3VCC

3

2

1

JP8

NUMEM

C29
1uF

R37
4.7k

R53
130

R38

47

C18
4.7uF

C27
4.7uF

R43

47

R54
47

C24
1uF

R42

47

C23
1uF

TP2

VRFT

C16
1uF

C15
1uF

R30

[not used]

R33

[not used]

C12
[not used]

R34

0

R36
[not used]

TP1

INPUT

R32
100

C14
1uF

R31

100

C11

10pF

1MEM

JP6

DELAY1

C32
1uF

+5V

C34
1uF

JP5

DELAY0

C13
1uF

J1
96-Pin Female

Q

4

Q

3

Q

2

Q

1

Q

0

F

F

E

F

5

6

7

8

9

10

11

12

13

29

28

27

26

25

24

23

22

21

2

0

1

9

1

8

1

7

1

6

1

5

1

4

D1

D0

PAF

PAE

GND

REN1

RCLK

REN2

OE

RS

WEN1

WCLK

WEN2/LD

VCC

Q8

Q7

Q6

Q5

3

0

3

1

1

2

3

4

D

8

D

7

D

6

D

5

D

4

D

3

D

2

Q

4

Q

3

Q

2

Q

1

Q

0

F

F

E

F

5

6

7

8

9

10

11

12

13

29

28

27

26

25

24

23

22

21

2

0

1

9

1

8

1

7

1

6

1

5

1

4

D1

D0

PAF

PAE

GND

REN1

RCLK

REN2

OE

RS

WEN1

WCLK

WEN2/LD

VCC

Q8

Q7

Q6

Q5

3

0

3

1

1

2

3

4

D

8

D

7

D

6

D

5

D

4

D

3

D

2

R

D

7

R

D

6

R

D

5

R

D

4

R

D

3

R

D

2

A

1

B

1

C

1

A

2

B

2

C

2

A

3

B

3

C

3

A

4

B

4

C

4

A

5

B

5

C

5

A

6

B

6

C

6

A

7

B

7

C

7

A

8

B

8

C

8

A

9

B

9

C

9

A

1

0

B

1

0

C

1

0

A

1

1

B

1

1

C

1

1

A

1

2

B

1

2

C

1

2

A

1

3

B

1

3

C

1

3

A

1

4

B

1

4

C

1

4

A

1

5

B

1

5

C

1

5

A

1

6

B

1

6

C

1

6

A

1

7

B

1

7

C

1

7

A

1

8

B

1

8

C

1

8

A

1

9

B

1

9

C

1

9

A

2

0

B

2

0

C

2

0

A

2

1

B

2

1

C

2

1

A

2

2

B

2

2

C

2

2

A

2

3

B

2

3

C

2

3

A

2

4

B

2

4

C

2

4

A

2

5

B

2

5

C

2

5

A

2

6

B

2

6

C

2

6

A

2

7

B

2

7

C

2

7

A

2

8

B

2

8

C

2

8

A

2

9

B

2

9

C

2

9

A

3

0

B

3

0

C

3

0

A

3

1

B

3

1

C

3

1

A

3

2

B

3

2

C

3

2

TP3

VRFB

L1

CHOKE

TP6

AGND

C20
1uF

J3

INPUT

R39
4.7k

C22
1uF

C28
1uF

+5V

+5V

TP7

+3VCC

D

4

D

3

D

2

D

1

D

0

R41
4.7k

R44
4.7k

C30
1uF

R52
100

C36
10pF

2MEM

MCREST

R56

47

D[0..7]

D[0..7]

100MHz

100MHz

C25
1uF

D3

LM4040BIZ-2.5

R50
100

C33

10pF

R51
100

C35

10pF

TP6

GND

R55

47

R33A

100

R33B

100

New Values:

R34 was 47 now 0

R36 was 75 now not used

R30 was 110 now not used

R33  was 91 now not used

C12 was 1uF now not used

R33A and R33B added 

between 

VRFT

and 

VRFB

2MEM

1MEM

R57
10k

+3VCC

JP9

PD

1

0

   

   

   

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Содержание ADC08200

Страница 1: ... Semiconductor December 2005 Rev 7 Evaluation Board Instruction Manual ADC08200 8 Bit 10 MSPS to 230 Msps Analog to Digital Converter with Internal Sample Hold 2001 2002 2005 National Semiconductor Corporation ...

Страница 2: ... Blank Page ...

Страница 3: ...rd 7 5 1 Software Installation 7 5 2 Setting up the ADC08200 Evaluation Board 7 5 2 1 Board Set up 7 5 2 1 1 Computer Mode Operation 7 5 2 1 2 Manual Mode Operation 8 5 2 2 Quick Check of Analog Functions 8 5 2 3 Quick Check of Software and Computer Interface Operation 8 5 2 4 Getting Consistent Readings 8 5 2 5 Jumper Information 9 5 2 6 Troubleshooting 9 6 0 Evaluation Board Specifications 9 7 0...

Страница 4: ... Blank Page 4 http www national com ...

Страница 5: ...t and running WaveVision software operating under Microsoft Windows Use program WAVEVSN2 EXE available at National Semiconductor s web site 7 Connect a signal of 1 6VP P amplitude from a 50 Ohm source to Analog Input BNC J3 The ADC input signal can be observed at TP1 Because of isolation resistor R32 and the scope probe capacitance the input signal at TP1 will not have the same frequency response ...

Страница 6: ...his 50 Ohm input is intended to accept a low noise sine wave signal of 1 6V peak to peak amplitude To accurately evaluate the ADC08200 dynamic performance the input test signal should be passed through a high quality bandpass filter 60dB minimum stop band attenuation as even the best signal sources do not provide a pure enough sine wave to properly evaluate an ADC The reference voltages for the AD...

Страница 7: ...e ADC08200 is available at the 96 pin Euro connector J1 The series resistors of R35 isolate the ADC from the load circuit to reduce noise coupling into the ADC This evaluation package was designed to be easy and simple to use and to provide a quick and simple way to evaluate the ADC08200 The procedures given here will help you to properly set up the board 4 5 Power Supply Connections 5 2 1 Board S...

Страница 8: ...rity and stability and that the sampling clock signal is extremely stable with minimal jitter 6 Adjust RV2 for a voltage of 0 27V to 0 33V at TP4 7 Adjust the signal source at Analog Input J3 for a signal amplitude of approximately 1 6VP P and check for the presence of that signal at TP1 This completes the testing of the analog portion of the evaluation board 5 2 3 Quick Check of Software and Comp...

Страница 9: ...after turning on power before trying to capture data Be sure positions JP2 JP7 and JP8 are wired Be sure that the Digital Interface Board is connected to a serial printer port and has power Problem Opening Comm Port or Error Setting Comm State errors mean that the comm port selected is not the one to which the eval board is connected Be sure the proper port is selected type ALT O Ascertain that an...

Страница 10: ... R33 not used C12 not used R34 0 R36 not used TP1 INPUT R32 100 C14 1uF R31 100 C11 10pF 1MEM JP6 DELAY1 C32 1uF 5V C34 1uF JP5 DELAY0 C13 1uF J1 96 Pin Female Q4 Q3 Q2 Q1 Q0 FF EF 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 D1 D0 PAF PAE GND REN1 RCLK REN2 OE RS WEN1 WCLK WEN2 LD VCC Q8 Q7 Q6 Q5 30 31 1 2 3 4 D8 D7 D6 D5 D4 D3 D2 Q4 Q3 Q2 Q1 Q0 FF EF 5 6 7 8 9 10 11 12 1...

Страница 11: ...C10H125FN U2B MC10H125FN U2C MC10H125FN U2D MC10H125FN R22 47 R18 47 C6 1uF R27 510 5 2V C1 1uF R20 47 100MHz R21 47 _______ 100MHz T1 T4 6T 19 18 13 12 14 D CC __ CE VCC S Q _ Q R VEE 15 20 17 10 3 4 9 12 8 D CC __ CE VCC S Q _ Q R VEE 7 2 5 10 R14 47 OUT __ IN IN 8 9 7 R26 510 R17 47 JP1 ADCCLk Y1 200MHz 5 2V R11 330 C5 1uF OUT __ IN IN 3 4 5 2 20 R15 47 OUT __ IN IN 13 14 15 R13 330 R12 47 14 8...

Страница 12: ...R52 100 Type 1206 26 2 R33A R33B 100 W Leaded 27 1 R53 130 Type 1206 28 1 R40 220 Type 1206 29 2 R10 R47 240 Type 1206 30 5 R1 R2 R11 R13 R46 330 Type 1206 31 5 R25 R26 R27 R28 R29 510 Type 1206 32 1 R4 1k Type 1206 33 1 R9 2 2k Type 1206 34 5 R24 R37 R39 R41 R44 4 7k Type 1206 35 1 R57 10k Type 1206 36 3 R30 R33 R36 not populated n a 37 1 R35 Resistor Pack 8 x 47 DigiKey 767 163 R47 ND 38 1 R49 R...

Страница 13: ... Connect 1 2 Divide Clock Oscillator Y1 frequency by 2 Connect 2 3 Use Clock Oscillator Y1 frequency without dividing it Default JP2 Jumper Memory Connect 1 2 Use one FIFO chip Connect 2 3 Use both FIFO chips Default hard wired position JP3 thru JP6 Not Used JP7 Jumper Divide Enable Connect 1 2 Use both FIFO chips divide FIFO read signal frequency by 2 Default hard wired position Connect 2 3 Use o...

Страница 14: ... D5 C18 ADC output D6 B19 ADC output D7 C19 ADC output D8 not used ADC output D9 not used ADC output D10 not used ADC output D11 not used GND A1 thru A24 A28 B28 C28 A31 B31 C31 Memory Read Clock B15 Reserved Signal B22 C22 C23 Reserved Power A25 A26 B25 B26 C25 C26 5V Logic Power Supply to Digital Interface Board Reserved Power 5 2V A29 B29 C29 Reserved Power 5V A32 B32 C32 14 http www national c...

Страница 15: ... Blank Page 15 http www national com ...

Страница 16: ...systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component in a life support device or system whose failure to perfor...

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