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NI Digital System Development Board User Manual

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The audio codec needs to be clocked from the Zynq on the MCLK pin. This master clock will
be used by the audio codec to establish the audio sampling frequency. This clock is required to
be an integer multiple of the desired sampling rate. The default settings require a master clock
of 12.288 MHz, resulting in a 48 kHz sampling rate. For other frequencies and their respective
configuration parameters, consult the SSM2603 datasheet.

The codec has two modes: master and slave, with the slave being default. In this mode, the
direction of the signals is specified in Table 25. When configured as master, the direction of
BCLK, PBLRC and RECLRC is inverted. In this mode, the codec generates the proper
frequencies for these clocks. Digilent recommends that the audio codec be used in slave mode,
because this tends to simplify the clocking scheme of the FPGA logic. No matter where the
clocks are generated, PBDAT needs to be driven out and RECDAT sampled in sync with them.
The master clock is always driven out of the Zynq.

The timing diagram of an I²S stream can be seen on Figure 19. Note the one-cycle delay of the
data stream with respect to the left/right clock changing state. Audio samples are transmitted
MSB first, noted as 1 in the diagram.

Figure 19.

I²S Timing Diagram

The digital mute signal (MUTE) is active-low, with a pull-down resistor. This means that when
not used in the design, it will stay low and the analog outputs of the codec will stay muted. To
enable the analog outputs, drive this signal high. It is important to note that the audio codec will
not receive or transmit any audio data until the MUTE signal is driven high.

To use the audio codec in a design with non-default settings, it needs to be configured over I2C.
The audio path needs to be established by configuring the (de)multiplexers and amplifiers in the
codec. Some digital processing can also be done in the codec. Configuration is read out and
written by accessing the register map via I2C transfers. The register map is described in the
SSM2603 datasheet.

Reset Sources

Power-on Reset

The Zynq supports an external power-on reset signal. The power-on reset is the master reset of
the entire chip. This signal resets every register in the device capable of being reset. The DSDB
uses this signal to hold the Zynq in reset until all power supplies are stable. The user can also
assert the Zynq power-on reset by pressing the red button labeled “PS-PORB”. This (or a power
cycle) is necessary whenever the boot mode is changed using SW8.

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Содержание ZYNQ XC7Z020-1CLG484C

Страница 1: ...Zynq development platform independent of NI ELVIS Contents Contents 1 Features 3 Hardware Components 5 Power Supplies 6 Input Power Monitoring 9 User Power Supplies 9 User Power Supplies Monitoring 10 Zynq AP SoC Architecture 11 Zynq Configuration 15 microSD Boot Mode 16 Quad SPI Boot Mode 16 JTAG Boot Mode 16 Connecting to NI ELVIS 16 SPI Flash 18 DDR3 Memory 19 USB UART Bridge Serial Port 20 mic...

Страница 2: ...ocessor Subsystem Reset 44 User IO Protection 44 Pmod Connectors 44 Standard Pmod 45 MIO Pmod 45 MXP Connector 46 Breadboards 47 NI ELVIS Analog Breadboard 48 FPGA Digital IO Breadboard 48 Power Breadboard 48 DSDB Programming Guide 48 Programming in LabVIEW FPGA 48 Programming in Multisim 53 Installation and Setup 62 What You Need to Get Started 62 Installation and Setup Instructions 63 ...

Страница 3: ...width peripheral controllers 1G Ethernet SDIO Low bandwidth peripheral controller SPI UART CAN I2C On chip analog to digital converter XADC Programmed using JTAG Quad SPI Flash or microSD Reprogrammable logic equivalent to Artix 7 FPGA 13 300 logic slices each with four 6 input LUTs and eight flip flops 560 KB of fast block RAM Four clock management tiles each with a phase locked loop PLL and mixe...

Страница 4: ...en 128 32 monochrome OLED Display Four digit 7 segment display USB HID connector for mice and keyboards Eight FPGA connected LEDs One processor connected LED Four push buttons Eight slide switches Expansion Connectors MXP Connector Breadboard with analog I O from NI ELVIS and digital I O from Zynq Two Pmod connectors with eight FPGA I O each One Pmod connector with eight Processor I O The DSDB is ...

Страница 5: ...Quad SPI Flash 20 USB HID Connector 21 USB JTAG Programming Circuitry USB UART Bridge 22 Eight FPGA Connected LEDs 23 Four Push Buttons 24 Eight Slide Switches 25 Three PMOD Connectors Two Routed to FPGA and One Routed to Processor ON OFF J13 1 5 10 15 20 25 30 35 40 45 50 55 60 1 5 10 15 20 25 30 35 40 45 50 55 60 A B C D E F G H I J A B C D E F G H I J DISP2 DISP1 MXP LINE IN MIC IN LINE OUT HPH...

Страница 6: ...re features are intended to be used for example drawing more power from the user supplies a power demanding FPGA configuration or connecting a USB device that needs more than 100 mA the DSDB board should be used as standalone with an external power supply When used as a standalone platform an external power supply should be used by plugging into the power jack J17 The supply must use a coax center...

Страница 7: ...verview Voltage regulator circuits from Analog Devices create the required 3 3 V 1 8 V 1 5 V and 1 0 V supplies from the main power input Table 1 provides additional information typical currents depend strongly on FPGA configuration and the values provided are typical of medium size speed designs ...

Страница 8: ...FPGA Auxiliary Ethernet I O USB OTG IC55 3 ADP5052 1 2 A 0 1 A to 0 5 A 1 5 V DDR3 IC55 4 ADP5052 1 2 A 0 1 A to 1 2 A 1 8 V XADC Analog IC26 5 ADP5052 200 mA 20 mA 3 3 V Audio Analog IC6 ADP150 150 mA 50 mA 10 V Analog Output Stage D28 C351 C349 15 mA 2 mA 5 V Analog Output Stage D29 C355 C356 15 mA 2 mA 1 25 V XADC Precision Reference IC27 ADR127 5 mA 50 A 2 5 V Reference for DAC and ADC IC61 AD...

Страница 9: ...trolled startup to limit inrush current In case the input supply voltage is outside the operating range of 4 6 V to 5 5 V or if the current consumption exceeds 4 4 A the TPS25940 will turn off the board power User Power Supplies The DSDB provides two user power supplies 5 V and 3 3 V The 5 V user supply is available at the MXP connector while the 3 3 V is accessible at the PMODs JA JB JC MXP conne...

Страница 10: ...rnal to the FPGA For more information on using the XADC core refer to the Xilinx document 7 Series FPGAs and Zynq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Converter It is also possible to access the XADC core directly using the PS via the PS XADC interface This interface is described in full in chapter 30 of the Zynq Technical Reference Manual The 3 3 V 5 V user voltages...

Страница 11: ... is fed into a current sense amplifier with a gain of 50 INA216A2 and divided by 5 before it is connected to the XADC inputs The equation below shows how to compute current from the XADC number Zynq AP SoC Architecture The Zynq AP SoC is divided into two distinct subsystems The Processing System PS and the Programmable Logic PL Figure 4 shows an overview of the Zynq AP SoC architecture with the PS...

Страница 12: ...y by the processor or via the JTAG port The PS consists of many components including the Application Processing Unit APU which includes 2 Cortex A9 processors Advanced Microcontroller Bus Architecture AMBA Interconnect DDR3 Memory controller and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins called Multiplexed I O or MIO pins Peripheral controllers th...

Страница 13: ... cores implemented in the PL can trigger interrupts to the processors connections not shown in Figure 4 and perform DMA accesses to DDR3 memory There are many aspects of the Zynq AP SoC architecture that are beyond the scope of this document For a complete and thorough description refer to the Zynq Technical Reference Manual available at www xilinx com Table 3 depicts the external components conne...

Страница 14: ...ual MIO 501 1 8 V Peripherals Pin ENET 0 SDIO 0 16 TXCK 17 TXD0 18 TXD1 19 TXD2 20 TXD3 21 TXCTL 22 RXCK 23 RXD0 24 RXD1 25 RXD2 26 RXD3 27 RXCTL 28 39 Unconnected 40 CCLK 41 CMD 42 D0 43 D1 44 D2 45 D3 46 Unconnected 47 CD 48 51 Unconnected 52 MDC 53 MDIO ...

Страница 15: ...ched and the previous state of the mode register is used This means that the DSDB needs a power cycle to register any change in the programming mode switch SW8 Next the BootROM copies an FSBL from the form of non volatile memory specified by the mode register to the 256 KB of internal RAM within the APU called On Chip Memory or OCM The FSBL must be wrapped up in a Zynq Boot Image in order for the ...

Страница 16: ...o either let the software begin executing or step through it line by line using Xilinx SDK It is also possible to directly configure the PL over JTAG independent of the processor This can be done using iMPACT or the Vivado Hardware Server The DSDB is configured to boot in Cascaded JTAG mode which allows the PS to be accessed via the same JTAG port as the PL It is also possible to boot the DSDB in ...

Страница 17: ...te that 5 V from this connector is also used to power the entire board The GND pins of the NI ELVIS connector the ground plane of the DSDB and the pins labeled GND on the breadboard headers are all connected For further information on the functionality of the pins on the NI ELVIS connector please refer to the NI ELVIS documentation Table 4 NI ELVIS breadboard connections NI ELVIS Pin Zynq Pin DIO0...

Страница 18: ...ts to the Zynq 7000 AP SoC supporting up to Quad I O SPI interface This requires connection to specific pins in MIO Bank 0 500 specifically MIO 1 6 8 as outlined in the Zynq datasheet Quad SPI feedback mode is used thus qspi_sclk_fb_out MIO 8 is left to freely toggle and is connected only to a 20K pull up resistor to 3 3 V This allows a QSPI clock frequency greater than FQSPICLK2 Table 5 NI ELVIS ...

Страница 19: ... data bits inside byte groups were swapped as well These changes are transparent to the user Appropriate Xilinx PCB guidelines were followed during design Both the memory chips and the PS DDR bank are powered from the 1 5 V supply The mid point reference of 0 75 V is created with a simple resistor divider and is available to the Zynq as external reference For proper operation it is essential that ...

Страница 20: ... also used as the controller for the Digilent USB JTAG circuitry but the USB UART and USB JTAG functions behave entirely independent of one another Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with the UART data transfers and vice versa The combination of these two features into a single device al...

Страница 21: ...vice towards the FPGA over two PS 2 ports Port 0 is always keyboard while port 1 is always mouse Hub support is not currently available so only a single mouse or keyboard can be used at any time HID Controller The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old style PS 2 bus The microcontroller behaves just like a PS 2 keyboard or mouse would This m...

Страница 22: ...the device ID This ID can be read by issuing a Read ID command 0xF2 Also a mouse sends its ID 0x00 right after the self test passed command which distinguishes it from a keyboard Keyboard PS 2 uses open collector drivers so the keyboard or an attached host device can drive the two wire bus if the host device will not send data to the keyboard then the host can use input only ports PS 2 style keybo...

Страница 23: ...s data to the host in 11 bit words that contain a 0 start bit followed by 8 bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit The keyboard generates 11 clock transitions at 20 to 30 kHz when the data is sent and data is valid on the falling edge of the clock Table 8 Keyboard Commands Command Action ED Set Num Lock Caps Lock and Scroll Lock LEDs Keyboard ret...

Страница 24: ...nd YS bits in the status byte are the sign bits a 1 indicates a negative number The magnitude of the X and Y numbers represent the rate of mouse movement the larger the number the faster the mouse is moving the XV and YV bits in the status byte are movement overflow indicators a 1 means overflow has occurred If the mouse moves continuously the 33 bit transmissions are repeated every 50ms or so The...

Страница 25: ... MAC Of these two GEM 0 can be mapped to the MIO pins where the PHY interfaces Since the MIO bank is powered from 1 8 V the RGMII interface uses 1 8 V HSTL Class 1 drivers For this I O standard an external reference of 0 9 V is provided in bank 501 PS_MIO_VREF Mapping out the correct pins and configuring the interface is handled by the PS preset part of the board definition files The MDIO bus is a...

Страница 26: ...on board quad SPI Flash This one time programmable OTP section is factory written and is separate from the regular Flash memory space It can be read out with the special OTP Read 0x4B command The MAC is located in the six bytes starting at address 0x20 The byte order is big endian so the most significant byte starts at the lower address The three most significant bytes correspond to the Digilent O...

Страница 27: ...ork Figure 8 Serial Interface Timing Diagram Figure 9 OLED Serial Interface Bit Ordering Table 11 OLED Signal Description Signal Description Polarity FPGA Pin RES Reset Active low E16 CS Chip select always active Active low N A D C Data high Command low Both H15 SCLK Serial Clock Active hig h J15 SDIN Serial Data Active hig h J17 VBAT Power enable for internal power supply Active low L17 VDD Power...

Страница 28: ...Send Display On command 0xAF Table 12 Timing Diagram Symbols and Parameters Symbol Parameter Min Typ Max Unit tcycle Clock Cycle Time 100 ns tAS Address Setup Time 15 ns tAH Address Hold Time 15 ns tCSS Chip Select Setup Time 20 ns tCSH Chip Select Hold Time 10 ns tDSW Write Data Setup Time 15 ns tDHW Write Data Hold Time 15 ns tCLKL Clock Low Time 20 ns tCLKH Clock High Time 20 ns tR Rise Time 40...

Страница 29: ...lor signals with the correct timing in order to produce a working display system VGA System Timing VGA signal timings are specified published copyrighted and sold by the VESA organization The following VGA system timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode Note For more precise information or for information on other VGA frequencies refer to...

Страница 30: ...nd the display surface the beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields Because cathode rays are composed of charged particles electrons they can be deflected by these magnetic fields Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surf...

Страница 31: ...l Typical displays use from 240 to 1200 rows and from 320 to 1600 columns The overall size of a display and the number of rows and columns determines the size of each pixel Figure 11 VGA Horizontal Synchronization Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location the DSDB uses 16 bits per pixel The controller must index into video memory ...

Страница 32: ...ctual VGA displays Figure 12 Signal Timings for a 640 pixel by 480 Row Display Using a 25 MHz Pixel Clock and 60 Hz Vertical Refresh A VGA controller circuit such as the one diagramed in Figure 13 decodes the output of a horizontal sync counter driven by the pixel clock to generate HS signal timings You can use this counter to locate any pixel location on a given row Likewise the output of a verti...

Страница 33: ...strain it to the correct PL pin to leave other devices on the CEC bus unaffected When operating as Sink the DDC function is required to be implemented so that a connected Source can read out important characteristics of the device This can be done by emulating an I2C capable EEPROM in programmable logic Likewise in Source mode DDC can be used to find out the capabilities of the connected display T...

Страница 34: ... 800 x 480 RGB display with a 24 bit color depth The touch panel size has been scaled to the LCD so that every point read from the touch panel can be converted to a RGB pixel on the TFT LCD Although the LCD and touch panel come as an assembly they have independent controllers and are driven separately LCD Display The LCD has an ILI6122 timing controller mounted on it which interfaces to the TFT di...

Страница 35: ...o use the LCD the DISP pin must be set to logic high This pin is an enable pin which allows the user to turn off the display without interrupting the timing and data flow When sending data to the display the following timing specifications must be respected Figure 14 Horizontal Timing 31 TFT_DISP Display enable active high 32 TFT_HS Horizontal synchronisation pulse 33 TFT_VS Vertical synchronisati...

Страница 36: ...nicate through an I2C protocol Similar to the LCD the touch connects to the board using a strip connector with the following pinout Horizontal pulse width Min thpw 1 CLKIN Typ CLKIN Max 40 CLKIN Horizontal back porch thbp 46 46 46 CLKIN Horizontal front porch thfp 16 210 354 CLKIN Table 17 Vertical Timing Vertical Input Timing Parameter Symbol Value Unit Min Typ Max Vertical display area tvd 480 H...

Страница 37: ...for the wake up sequence must be driven low for 0 5 to 1 ms The reason for this short period is that the INT port will act as an interrupt output port after the wake up The following registers can be used in order to obtain a minimal functionality of the touch panel This is the device mode register which is configured to determine the current mode of the chip Read Write This register describes MSB...

Страница 38: ... Event Flag 00b Press Down 01b Lift Up 10b Contact 11b No event 5 4 Reserved 3 0 Touch X Position 11 8 MSB of Touch X Position in pixels Table 21 X LSB Register Address Bit Address Register Name Description 04h 1Ch 7 0 Touch X Position 7 0 LSB of the Touch X Position in pixels Table 22 Y MSB Register Address Bit Address Register Name Description 05h 1Dh 7 4 Touch ID 3 0 Touch ID of Touch Point 0 4...

Страница 39: ...ce clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL in order to cut the cost of including a dedicated oscillator for this purpose Keep in mind that CLK125 will be disabled when the Ethernet PHY IC1 is held in hardware reset by driving the PHYRSTB signal low Basic I O The DSDB includes a four digit seven segment display eight slide switches four push buttons and e...

Страница 40: ...parate as shown in Figure 17 The common anode signals are available as four digit enable input signals to the 4 digit display The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG For example the four D cathodes from the four digits are grouped together into a single circuit node called CD These seven cathode signals are available as inp...

Страница 41: ...continuously illuminated all four digits should be driven once every 1 to 16ms for a refresh frequency of about 1 kHz to 60Hz For example in a 62 5Hz refresh scheme the entire display would be refreshed once every 16ms and each digit would be illuminated for 1 4 of the refresh cycle or 4ms The controller must drive low the cathodes with the correct pattern when the corresponding anode signal is dr...

Страница 42: ...a is transferred via the I S protocol Configuration is done over an I2C bus The device address of the SSM2603 is 0011010b All digital I O are 3 3 V level and connect to a 3 3 V powered FPGA bank Table 24 Analog Audio Signals Audio Jack Description Channels Color J7 Headphone Out Stereo Black J8 Line Out Stereo Light Green J10 Microphone In Mono Pink J11 Line In Stereo Light Blue Table 25 Digital A...

Страница 43: ...stream with respect to the left right clock changing state Audio samples are transmitted MSB first noted as 1 in the diagram Figure 19 I S Timing Diagram The digital mute signal MUTE is active low with a pull down resistor This means that when not used in the design it will stay low and the analog outputs of the codec will stay muted To enable the analog outputs drive this signal high It is import...

Страница 44: ...Moreover the 33 PTC prevents short circuits that can occur if the user accidentally drives a signal that is supposed to be used as an input The SN74CBT3384C provides the possibility to connect input signal levels up to 5 V by limiting the voltage going into the Zynq pin to 3 3 V It should be noted that output signals are only compatible with 3 3 V standards Moreover this Bus Switch disconnects the...

Страница 45: ...od The standard Pmod connectors are connected to the PL of the Zynq via the protection circuit described in section User IO Protection which limits the minimum pulse width to 20 ns 50 MHz MIO Pmod The MIO Pmod connector is connected to the MIO but in the PS of the Zynq via protection circuitry Like the standard Pmod connector this circuit adds protection at the cost of maximum switching speed Sinc...

Страница 46: ...able ecosystem of educational add ons This connector was included on the DSDB to provide the Zynq with access to these add ons Figure 21 shows the signals on the DSDB MXP connector Figure 21 MXP Pins Table 27 MXP Pin Descriptions Signal Name Reference Direction Description 5V DGND Output 5 V power output AI 0 3 AGND Input 0 5 V referenced single ended analog input channels AO 0 1 AGND Output 0 5 V...

Страница 47: ...onnected to channel 1 and so on The serial interface of the ADC is connected to the programmable logic of the Zynq For the Zynq pin assignments of DIO0 DIO15 UART RX UART TX the DAC serial bus and the ADC serial bus see the Master XDC available on the DSDB Digilent Resource Center Breadboards The DSDB board includes a large solderless prototyping area composed of 165 x 35mm breadboard and 165 x 10...

Страница 48: ...e section User Power Supplies and User Power Supplies Monitoring for a detailed description Power Breadboard he Power Breadboard makes available to the user the power supplies generated by NI ELVIS including the positive and negative programmable supplies 15 V and 15 V For detailed information visit the NI ELVIS II Series User Manual and NI ELVIS II Series Specifications available at ni com manual...

Страница 49: ...GA_Design lvproj Creating an FPGA Target VI 1 In the Project Explorer window right click My Computer and select New Targets and Devices 2 In the Add Targets and Devices on My Computer window select New target or device expand Digilent and highlight Digital Systems Development Board Click OK The target is discovered and the target and target properties are loaded into the project tree 3 In the Proj...

Страница 50: ...rer window FPGA Target DSDB Digital Systems Development Board tree view select BTN0 and LED2 and drag them onto the block diagram 7 In the LabVIEW block diagram wire BTN0 output to the LED2 input 8 Add a While Loop around the resources 9 Wire a false constant to the stop condition of the While Loop as shown below 10 Save the VI as FPGA_Design vi ...

Страница 51: ...DL code and generates a bitstream file that is downloaded into the FPGA configuration storage The Generating Intermediate Files window opens and displays the compilation progress The LabVIEW FPGA Compile Server window opens and runs Choose compile locally The compilation takes several minutes See an image of the compile server window below 5 When the compilation finishes click Stop Server to close...

Страница 52: ... up and down LED0 should correspondingly light and turn off 8 Press button BTN0 LED2 should correspondingly light and turn off More DSDB examples can be found in the LabVIEW Example Finder 1 In LabVIEW Click Help Find Examples 2 Click the Search tab 3 Enter dsdb 4 Open one of the provided examples and follow the included instructions ...

Страница 53: ...e pressed simultaneously Prerequisites Hardware Digital System Development Board Software Multisim 14 0 1 or later LabVIEW 2015 FPGA Module Xilinx Tools Vivado 2014 4 or later OR Vivado HL WebPACK Installation Instructions 1 Install Multisim 14 0 1 or later 2 Install LabVIEW 2015 FPGA Module Xilinx Tools Vivado 2014 4 or later 3 Install the Digilent drivers a Navigate to C NIFPGA Programs and sele...

Страница 54: ...54 ni com NI Digital System Development Board User Manual Procedure Creating a Project 1 In Multisim select File New 2 Click PLD Design then click Create ...

Страница 55: ...NI Digital System Development Board User Manual National Instruments 55 3 Click the Use standard configuration down arrow and select your board Click Next ...

Страница 56: ...al 4 Enter Introduction to Digital Electronics in the PLD design name field and click Next 5 The New PLD Design dialog allows you to select which peripherals you will use in your design Ensure the LED LED0 and the push button BTN0 are selected Click Finish ...

Страница 57: ...NI Digital System Development Board User Manual National Instruments 57 6 The selected connectors are placed on the workspace ...

Страница 58: ...Manual Create a PLD Schematic in Multisim 1 Select Place Component 2 Select an AND2 gate located in the PLD Logic group Logic_gates family and click OK 3 Place another connector for the AND gate input by clicking the Input connector icon on the toolbar ...

Страница 59: ...ng the digital logic from the PLD schematic Programming the connected PLD Allows students to deploy the design directly to the FPGA Generate and save a programming file Students can generate a bitfile that can be used to program hardware later Generate and save the VHDL This option exports the VHDL netlist allowing students to view the VHDL code You can import the VHDL code in the Xilinx environme...

Страница 60: ...Manual In this tutorial you will program the FPGA board directly from the Multisim environment 1 Select Transfer Export to PLD 2 Click Program the connected PLD and then click Next 3 In the Select a tool to use area select the Xilinx tool for your board ...

Страница 61: ...t support file path containing spaces for the XDC file In these cases you will get an illegal file or directory name error when trying to export the design If this happens copy the DSDB xdc file stored in the installation folder Program Files National Instruments Circuit Design Suite 14 0 1 pldconfig to a local path such as C temp Next change the Xilinx user constraint file xdc in the Multisim PLD...

Страница 62: ... Board The DSDB containing the following The DSDB Standard USB type A to mini B cable DSDB software readme and user documentation NI ELVIS II Series Benchtop Workstation AC DC power supply high speed USB 2 0 cable NI ELVISmx 4 0 or later software CD and the NI ELVIS II Series Quick Start Guide Optional 15 VDC 650 mA power adapter Multisim 14 0 1 or LabVIEW 2015 or NI LabVIEW 2015 and the LabVIEW F...

Страница 63: ...O THE ACCURACY OF THE INFORMATION CONTAINED HEREIN AND SHALL NOT BE LIABLE FOR ANY ERRORS U S Government Customers The data contained in this manual was developed at private expense and is subject to the applicable limited rights and restricted data rights as set forth in FAR 52 227 14 DFAR 252 227 7014 and DFAR 252 227 7015 Installation and Setup Instructions To install and set up the DSDB comple...

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