National Instruments USB-6210, Руководство пользователя

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Chapter 7 PFI
© National Instruments Corporation 7-5 NI USB-621x User Manual
Ass u me that an inp u t terminal has been low for a long time. The inp u t
terminal then changes from low to high, b u t glitches several times. When
the filter clock has sampled the signal high on N consec u tive edges, the low
to high transition is propagated to the rest of the circ u it. The val u e of N
depends on the filter setting; refer to Table 7-1.
The filter setting for each inp u t can be config u red independently. On power
u p, the filters are disabled. Fig u re 7-4 shows an example of a low to high
transition on an inp u t that has its filter set to 125 ns (N = 5).
Figure 7-4. Filter Example
Enabling filters introd u ces jitter on the inp u t signal. For the 125 ns and
6.425
μ
s filter settings, the jitter is u p to 25 ns. On the 2.56 ms setting, the
jitter is u p to 10.025
μ
s.
Refer to the KnowledgeBase doc u ment, Digital Filtering with M Series ,
for more information abo u t digital filters and co u nters. To access this
KnowledgeBase, go to
ni.com/info
and enter the info code
rddfm s
.
Table 7-1. Filters
Filter Setting
N (Filter Clocks
Needed to
Pass Signal)
Pulse Width
Guaranteed to
Pass Filter
Pulse Width
Guaranteed to
Not Pass Filter
125 ns 5 125 ns 100 ns
6.425
μ
s 257 6.425
μ
s 6.400
μ
s
2.56 ms ~101,800 2.56 ms 2.54 ms
Disabled — — —
1 2 3 1 4 1 2 3 4 5
PFI Termin a l
Filter Clock
(40 MHz)
Filtered Inp u t
Filtered inp u t goe s high
when termin a l i s sa mpled
high on five con s ec u tive
filter clock s .