Chapter 2
Using the Module
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National Instruments Corporation
2-25
Figure 2-19 shows how the ADCs from each channel are connected through to the
PXI Express bus. Data from the ADCs are adjusted in hardware to remove offset and gain
errors. Then, if required, the data is filtered and decimated to match the specified acquisition
rate. Finally, the data is placed into a FIFO where it is transferred through PCI Express to the
host computer memory.
Figure 2-19.
NI PXIe-4330/4331 Digital Back End Block Diagram
Timing and triggering of the acquisition is handled by an onboard timing and triggering
controller. This controller configures an onboard DDS clock generator to provide an
oversample clock to the ADCs in order to acquire data at the specified rate. The DDS clock
can be generated either using an onboard oscillator or using the 100 MHz backplane clock
provided by PXI Express. Running the DDS clock from the 100 MHz backplane clock allows
for synchronization of multiple NI PXIe-4330/4331 modules. In addition to sending and
receiving triggers from the PXIe backplane, the NI PXIe-4330/4331 can also be configured
to generate an Analog Trigger event from the digitized analog data of its ADCs.
Signal Acquisition Considerations
This section contains information about signal acquisition concepts, including software
scaling and equations, Delta-Sigma converters, Nyquist frequency and bandwidth, timing,
triggering, and synchronization.
Gain &
Offset
Correction
Digital
Filtering &
Decimation
FIFO
PCIe
Interface
Logic
Analog
Trigger
Timing &Triggering
Controller
DDS Clock
Generation
PCIe Interf
ace
PXIe Cloc
ks and
T
riggers
PXI-Express Bus
ADC 0
ADC 7
