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Chapter 3
Signal Acquisition
Triggering and Filter Delay
The PXIe-4480/4481 interprets triggers based on where they occur in time. The hardware
automatically compensates for its group delay such that data from this module will line up
closely in time with the occurrence of the trigger event. However, the group delay affects how
long it takes to receive data when starting an acquisition. Since linear phase FIR filters are used
in the digital filtering, it is necessary to wait for the filter group delay to elapse after sending a
sync pulse before the start trigger can be correctly handled in time. Step 6 in the
section allows NI-DAQmx to handle this delay automatically. After the digital
start trigger, you cannot read data for the first sample in software until the digital filter group
delay has elapsed. Therefore, it takes a total of twice the digital filter group delay to start an
acquisition. You can insert additional time between when the sync pulse occurs and when the
start trigger occurs. This will not affect the time it takes before samples are available after the
start trigger, which is always the group delay time. Group delay time increases as sample rates
decrease.
Synchronization
Some applications require tight synchronization between input and output operations on
multiple modules. Synchronization is important to minimize skew between channels and to
eliminate clock drift between modules in long-duration operations. You can synchronize the
analog input operations on two or more PXIe-4480/4481 modules to extend the channel count
for your measurements. In addition, the PXIe-4480/4481 can synchronize with certain DSA
modules, such as the PXIe-449x modules, using Reference Clock Synchronization.
Reference Clock Synchronization
With reference clock synchronization, master and slave modules generate their ADC
oversample clock from the shared 100 MHz reference clock on the PXIe backplane
(PXIe_CLK100). The backplane supplies an identical copy of this clock to each peripheral slot.
In addition, multiple chassis can be synchronized by using a timing and synchronization board
to lock the 100 MHz clock across chassis.
When you acquire data from multiple modules within the same task, NI-DAQmx will
automatically handle all of the Reference Clock Synchronization details required to synchronize
the modules within the task. This is known as a Multidevice Task. Refer to the
DSA, SC Express,
and X Series Multidevice Tasks
topic in the
NI-DAQmx Help
to determine with which modules
the PXIe-4480/4481 can operate in a Multidevice Task.
