National Instruments PCIe-5774 Скачать руководство пользователя страница 13 | Manualshive

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National Instruments PCIe-5774 Скачать руководство пользователя страница 13

Figure 7. PCIe-5774 Block Diagram

EXTERNAL REF/SCLK

CLK IN SMA

AI1 SMA

ADC12DJ3200
Dual 12-bit, 3.2 GS/s
Single 12-bit, 6.4 GS/s

AI0 SMA

ANALOG INPUT

Input Range

Selection

Adapter Module

Connector

CLOCKING

Input Range

Selection

Filter

Filter

Offset

Offset

Amplifier

INPUT TRIGGER

OUTPUT TRIGGER

TRIG IN SMA

TRIG OUT SMA

Amplifier

Comparator

Threshold

DAC

Component-Level Intellectual Property (CLIP)

The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
•

User-defined CLIP

allows you to insert HDL IP into an FPGA target, enabling VHDL

code to communicate directly with an FPGA VI.

•

Socketed CLIP

provides the same IP integration of the user-defined CLIP, but it also

allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.

The PCIe-5774 ships with socketed CLIP items that add module I/O to the LabVIEW project.

Making a Measurement with LabVIEW

1.

Launch LabVIEW.

PCIe-5774 Getting Started Guide

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© National Instruments

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Содержание PCIe-5774

Страница 1: ...e 5774 Kit Contents 3 Preparing the Environment 3 Installing the Software and Driver 4 Installing the PCIe 5774 4 Installing the Ferrite on the DIO Cable 5 PCIe 5774 Front Panel and Pinout 6 Configuri...

Страница 2: ...Available at ni com manuals Contains information about the FPGA module front panel connectors and I O programming instructions and I O component level IP CLIP LabVIEW Examples Available in NI Example...

Страница 3: ...ge when the device is not in use PCIe 5774 Kit Contents The following items are included in the device kit PCIe 5774 Documentation Maintain Forced Air Cooling Note to Users PCIe 5774 Getting Started G...

Страница 4: ...or installation instructions and information about getting started with the LabVIEW FPGA Module Documentation for the LabVIEW FPGA Module is available at ni com manuals 3 Optional Install the LabVIEW...

Страница 5: ...7 Connect the 6 pin PCI Express power connector from the power supply to the PCIe 5774 8 Replace any access panels on the computer case 9 Power on your computer Installing the Ferrite on the DIO Cable...

Страница 6: ...rrite Bead Installation 1 2 1 Molex Nano Pitch I O connector 2 Ferrite PCIe 5774 Front Panel and Pinout PCIe 5774 Front Panel The following figure shows the PCIe 5774 front panel 6 ni com PCIe 5774 Ge...

Страница 7: ...ont Panel PCIe 5774 AI 0 AI 1 REF CLK IN TRIG IN TRIG OUT DIO 5Vpp MAX 6V MAX 3 3V LVTTL 3V MAX The following table describes the signal connections for the PCIe 5774 PCIe 5774 Getting Started Guide N...

Страница 8: ...Standard SMA female connector Analog input connection AI 1 REF CLK IN Standard SMA female connector Input for an external Reference Clock or Sample Clock TRIG IN Standard SMA female connector Analog...

Страница 9: ...3 GND MGT Tx 2 MGT Tx 2 GND MGT Tx 3 MGT Tx 3 GND Reserved The following table lists the available pins on the DIO connector Signal Type Direction MGT Tx 0 3 1 Xilinx UltraScale GTH Output MGT Rx 0 3...

Страница 10: ...e MAX toolbar The MAX self test performs a basic verification of hardware resources FlexRIO Examples FlexRIO includes several example applications for LabVIEW These examples serve as interactive tools...

Страница 11: ...V 12 V GPIO Configuration GPIO MGTs Reference Clock Power Supplies Flash FPGA Triggers Clk 100 Gen3 x8 PCIe 12 V 3 3 V 12 V Clk 10 Module Clocking Synchronization PLL DRAM Bank 0 2 GB DRAM Bank 1 2 GB...

Страница 12: ...Reference Clock Power Supplies Flash FPGA Triggers Clk 100 Gen3 x8 PCIe 12 V 3 3 V 12 V Clk 10 Module Clocking Synchronization PLL DRAM Bank 0 2 GB DRAM Bank 1 2 GB Synchronization Connector PCIe Conn...

Страница 13: ...n FlexRIO devices support two types of CLIP user defined and socketed User defined CLIP allows you to insert HDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI Socke...

Страница 14: ...are a Reference Clock and triggers between the PCIe 5774 and another PCI Express FlexRIO device You also can use the compact synchronization cable for PCIe and a RTSI adapter part number 147008A 01L t...

Страница 15: ...nd of the compact synchronization cable for PCIe into the closest synchronization connector on the RTSI adapter 5 Connect one RTSI female connector on the RTSI cable to the RTSI male connector on the...

Страница 16: ...system 2 Launch MAX and perform the self test again 3 Power off the chassis 4 Reinstall the failed module in a different slot 5 Power on the chassis 6 Perform the self test again Where to Go Next Refe...

Страница 17: ...ct registration facilitates technical support and ensures that you receive important information updates from NI NI corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759...

Страница 18: ...ments EULAs and third party legal notices in the readme file for your NI product Refer to the Export Compliance Information at ni com legal export compliance for the NI global trade compliance policy...

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