![background image](http://html1.mh-extra.com/html/national-instruments/pcie-5763/pcie-5763_getting-started-manual_709880009.webp)
Figure 4. Carrier Block Diagram (KU035)
DIO Connector
(Front Panel)
Adapter Module
Connector
+5 V
+1.8 V
+12 V
GPIO
Configuration, GPIO
MGTs
Reference Clock
Power Supplies
Flash
FPGA
Triggers
Clk 100
Gen3 x8 PCIe
+12 V, +3.3 V
+12 V
Clk 10
Module Clocking
Synchronization
PLL
DRAM Bank 0
(2 GB)
DRAM Bank 1
(2 GB)
Synchronization
Connector
PCIe
Connectors
The following figure shows a block diagram of the carrier portion of the PCIe-5763 (KU040
and KU060 FPGA versions).
PCIe-5763 Getting Started Guide
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© National Instruments
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