National Instruments NI PXIe-1082 Скачать руководство пользователя

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National Instruments

8-Slot NI PXIe-1082 Backplane Installation Guide

Hybrid Slot Pinouts

Table 9.

XP3 Connector Pinout for the System Timing Slot

Pin

PXIe

PXIe_CLK100-

GND

PXIe_

PXIe_SYNC100-

GND

PXIe

PXIe_DSTARC-

GND

PRSNT#

PWREN#

GND

PXIe

PXIe_DSTARB-

GND

PXIe

PXIe_DSTARA-

GND

SMBDAT

SMBCLK

GND

RSV

GND

RSV

GND

MPWRGD*

PERST#

GND

RSV

GND

1RefClk-

GND

1PETp0

1PETn0

GND

1PERp0

1PERn0

GND

1PETp1

1PETn1

GND

1PETp2

1PETn2

GND

1PERp2

1PERn2

GND

1PERp1

1PERn1

GND

1PETp3

1PETn3

GND

1PERp3

1PERn3

GND

1PETp4

1PETn4

GND

1PETp5

1PETn5

GND

1PERp5

1PERn5

GND

1PERp4

1PERn4

GND

1PETp6

1PETn6

GND

1PERp6

1PERn6

GND

1PETp7

1PETn7

GND

RSV

GND

RSV

GND

1PERp7

1PERn7

GND

Table 10.

XP4 Connector Pinout for the System Timing Slot

Pin

GND

GA4

GA3

GA2

GA1

GA0

GND

5Vaux

GND

SYSEN#

WAKE#

ALERT#

GND

12V

GND

3.3V

GND

PXI_TRIG3

PXI_TRIG4

PXI_TRIG5

GND

PXI_TRIG6

GND

PXI_TRIG2

GND

ATNLED

PXI_CLK10_IN

PXI_CLK10

GND

PXI_TRIG1

PXI_TRIG0

ATNSW#

GND

PXI_TRIG7

GND

PXIe_SYNC_CTRL

GND

RSV

PXI_LBL6

PXI_LBR6

GND

Table 11.

P1 Connector Pinout for the Hybrid Slot

Pin

GND

REQ64#

ENUM#

3.3V

GND

AD[1]

V(I/O)

AD[0]

ACK64#

GND

3.3V

AD[4]

AD[3]

AD[2]

GND

AD[7]

GND

3.3V

AD[6]

AD[5]

GND

3.3V

AD[9]

AD[8]

M66EN

C/BE[0]#

GND

AD[12]

GND

V(I/O)

AD[11]

AD[10]

GND

3.3V

AD[15]

AD[14]

GND

AD[13]

GND

Содержание NI PXIe-1082

Страница 1: ...Local Bus 6 PXI Trigger Bus 6 System Reference Clock 7 PXIe_SYNC_CTRL 9 Mechanical Requirements 10 Mounting 10 Dimensions 11 Cooling 11 Handling 12 Electrical Requirements 13 PXI Connectors 13 Power 14 Connector J37 14 Connector J36 16 Connector J35 16 Connectors J2 J3 and J4 17 Backplane Specifications 17 System Synchronization Clock PXI_CLK10 PXIe_CLK100 PXIe_SYNC100 Specifications 18 10 MHz Sys...

Страница 2: ...ARA PXIe DSTARB PXIe DSTARC 19 Pinouts 20 System Controller Slot Pinouts 21 System Timing Slot Pinouts 22 Hybrid Slot Pinouts 23 NI PXIe 1082 Backplane Overview This section provides an overview of the backplane features for the NI PXIe 1082 chassis Figure 1 shows the backplane Figure 1 8 Slot NI PXIe 1082 Backplane ...

Страница 3: ...system slot as defined by the CompactPCI Express and PXI Express specifications It has three system controller expansion slots for system controller modules that are wider than one slot These slots allow the system controller to expand to the left to prevent the system controller from using peripheral slots The backplane routes the first x4 PCI Express link from the system slot directly to slot 2 ...

Страница 4: ... to the PXI Express Specification for details The PXI peripheral communicates through the backplane 32 bit PCI bus A CompactPCI 32 bit peripheral on the backplane 32 bit PCI bus The hybrid peripheral slots provide full PXI Express functionality and 32 bit PXI functionality except for PXI Local Bus The hybrid peripheral slot connects only to PXI Local Bus 6 left and right PXI Express Peripheral Slo...

Страница 5: ...ed PXI Star trigger connected to every slot Refer to Figure 3 for details The system timing slot has a pin PXI_CLK10_IN through which a system timing module can source a 10 MHz clock to which the backplane phase locks Refer to the System Reference Clock section for details The system timing slot has a pin PXIe_SYNC_CTRL through which a system timing module can control the PXIe_SYNC100 timing Refer...

Страница 6: ...ific to each adjacent peripheral module to evaluate local bus compatibility PXI Trigger Bus All slots on the same PXI bus segment share eight PXI trigger lines You can use these trigger lines in a variety of ways For example you can use triggers to synchronize the operation of several different PXI peripheral modules In other applications one module in the system timing slot can control carefully ...

Страница 7: ...ial pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_CLK100 so that when there is no peripheral or a peripheral that does not connect to PXIe_CLK100 no clock is being driven on the pair to that slot Refer to Figure 5 for a termination example Figure 5 CLK100 Termination An independent buffer drives PXIe_SYNC100 to each peripheral slot The differential ...

Страница 8: ...section for the specification information for an external clock provided on the PXI_CLK10_IN pin of the system timing slot You also can drive a 10 MHz clock on connector J36 Refer to Figure 11 for the location of this connector When a 10 MHz clock is detected on this connector the backplane automatically phase locks the PXI_CLK10 PXIe_CLK100 and PXIe_SYNC100 signals to this external clock and dist...

Страница 9: ...fer to Table 9 XP3 Connector Pinout for the System Timing Slot for the system timing slot pinout Refer to the Backplane Specifications section for the PXIe_SYNC_CTRL input specifications By default a high level detected by the backplane on the PXIe_SYNC_CTRL pin causes a synchronous restart for the PXIe_SYNC100 signal On the next PXI_CLK10 edge the PXIe_SYNC100 signal restarts This allows several ...

Страница 10: ...ng holes for proper backplane support Eight mounting holes on top of the backplane have plated annular pads on the back of the backplane Use these mounting holes to connect the backplane ground to the chassis in which the backplane is mounted If you do not want to connect the backplane ground to the chassis use insulated washers at these mounting holes Refer to Figure 11 for the mounting hole posi...

Страница 11: ...to the top of the PXI modules You must determine the airflow requirements for your system based on the PXI Hardware Specification The backplane must be adequately cooled to function reliably Ensure that the components shown in Figure 9 are kept below their maximum case temperatures throughout the operating range 0 89 in 22 61 mm 0 125 in 3 18 mm 5 933 in 150 70 mm 0 122 in 3 10 mm 0 375 in 9 53 mm...

Страница 12: ...al hazards leave the chassis powered off until you finish installing the PXI controller and modules Caution Electrostatic discharge can damage your equipment To avoid such damage discharge the static built up on your body by touching a grounded metal object before handling the PXI equipment Then touch the antistatic plastic package containing the backplane to a metal part of your PXI chassis befor...

Страница 13: ...rdware Specification and PXI Express Hardware Specification Figure 10 shows the connectors Figure 10 PXI Connectors Figure 11 Backplane Power and J36 Connectors 1 Card Cage Thermistor Connectors x3 2 Slot 1 Controller Slot 3 PXI Express Peripheral Slots 2 to 3 4 System Timing Slot 4 5 Hybrid Peripheral Slots 5 to 8 6 Power Button Connector 1 Connector J36 2 Connector J37 1 1 1 2 4 3 5 6 2 1 ...

Страница 14: ...voltage sensing only Providing current through these pins may damage the backplane If your power supply has voltage sensing use these pins otherwise leave them unconnected Pins with power plane in the description are connected to the backplane s internal power planes and are suitable for carrying current Note Tyco Electronics manufactures the J37 mating connector which you can order with part numb...

Страница 15: ...ock No 10 SMBDAT Backplane SMBus data No 11 SMBALERT Backplane SMBus alert No 12 PS_ON From system slot J18 pin D2 No 13 PS_OK To system slot from power supply Yes 14 LED1 J35 pin 3 No 15 LED2 J35 pin 4 No 16 GND Ground plane Yes 17 12V 12 V power plane Yes 18 GND Ground plane Yes 19 OVERTEMP Alert of over temperature condition in card cage No 20 12V_FAN To pin 7 of test header W1 No 21 GND Ground...

Страница 16: ...and LED You do not need to connect anything to J35 for basic backplane power up Refer to Table 3 for the pin descriptions The power button PWRBTN signal is a momentary pushbutton signal that tells the system controller to enable or inhibit the power supply You can use signals LED1 and LED2 to drive a bicolor LED in the power switch but you also can use these signals to carry another digital signal...

Страница 17: ...nector for J2 J3 and J4 is Molex part number 50 57 9402 Backplane Specifications Size 3U sized one system slot with three system expansion slots and 7 peripheral slots Compliant with IEEE 1101 10 mechanical packaging PXI Express specification compliant Accepts both PXI Express and CompactPCI PICMG 2 0 R 3 0 3U modules Backplane bare board material UL 94 V 0 Recognized Backplane connectors Conforms...

Страница 18: ... Reference Clock PXIe_CLK100 and PXIe_SYNC100 Maximum slot to slot skew 100 ps Accuracy 25 ppm max guaranteed over the operating temperature range Maximum jitter 3 ps RMS phase jitter 10 Hz to 12 kHz range 2 ps RMS phase jitter 12 kHz to 20 MHz range Duty factor for PXIe_CLK100 45 to 55 Absolute single ended voltage swing When each line in the differential pair has 50 Ω termination to 1 30 V or Th...

Страница 19: ...ed by backplane 1 ps RMS phase jitter 10 Hz to 1 MHz range PXIe_SYNC_CTRL VIH 2 0 to 5 5 V VIL 0 to 0 8 V PXI Star Trigger Maximum slot to slot skew 250 ps Backplane characteristic impedance 65 Ω 10 Note For PXI slot to PXI Star mapping refer to the System Timing Slot section of Chapter 1 Getting Started in the NI PXIe 1082 User Manual Note For other specifications refer to the PXI 1 Hardware Spec...

Страница 20: ...Controller slot Table 6 shows the XP3 Connector Pinout for the System Controller slot Table 7 shows the XP4 Connector Pinout for the System Controller slot Table 8 shows the TP2 Connector Pinout for the System Timing slot Table 9 shows the XP3 Connector Pinout for the System Timing slot Table 10 shows the XP4 Connector Pinout for the System Timing slot Table 11 shows the P1 connector pinout for th...

Страница 21: ...ETn0 GND 4PERp0 4PERn0 GND 4PETp1 4PETn1 GND 4 4PETp2 4PETn2 GND 4PERp2 4PERn2 GND 4PERp1 4PERn1 GND 5 4PETp3 4PETn3 GND 4PERp3 4PERn3 GND RSV RSV GND 6 RSV RSV GND RSV RSV GND RSV RSV GND 7 RSV RSV GND RSV RSV GND RSV RSV GND 8 RSV RSV GND RSV RSV GND RSV RSV GND 9 RSV RSV GND RSV RSV GND RSV RSV GND 10 RSV RSV GND RSV RSV GND RSV RSV GND Table 6 XP3 Connector Pinout for the System Controller Slo...

Страница 22: ... RSV PXI_LBR6 GND Table 8 TP2 Connector Pinout for the System Timing Slot Pin A B ab C D cd E F ef 1 PXIe_DSTARC0 PXIe_DSTARC0 GND PXIe_DSTARC8 PXIe_DSTARC8 GND PXIe_DSTARB8 PXIe_DSTARB8 GND 2 PXIe_DSTARA0 PXIe_DSTARA0 GND PXIe_DSTARC9 PXIe_DSTARC9 GND PXIe_DSTARA8 PXIe_DSTARA8 GND 3 PXIe_DSTARB0 PXIe_DSTARB0 GND PXIe_DSTARC1 PXIe_DSTARC1 GND PXIe_DSTARA9 PXIe_DSTARA9 GND 4 PXIe_DSTARB1 PXIe_DSTAR...

Страница 23: ...1PERn4 GND 9 1PETp6 1PETn6 GND 1PERp6 1PERn6 GND 1PETp7 1PETn7 GND 10 RSV RSV GND RSV RSV GND 1PERp7 1PERn7 GND Table 10 XP4 Connector Pinout for the System Timing Slot Pin Z A B C D E F 1 GND GA4 GA3 GA2 GA1 GA0 GND 2 GND 5Vaux GND SYSEN WAKE ALERT GND 3 GND 12V 12V GND GND GND GND 4 GND GND GND 3 3V 3 3V 3 3V GND 5 GND PXI_TRIG3 PXI_TRIG4 PXI_TRIG5 GND PXI_TRIG6 GND 6 GND PXI_TRIG2 GND ATNLED PX...

Страница 24: ...CK 5V TMS TDO TDI GND 1 GND 5V 12V TRST 12V 5V GND Table 12 XP3 Connector Pinout for the Hybrid Slot Pin A B ab C D cd E F ef 1 PXIe_CLK100 PXIe_CLK100 GND PXIe_SYNC100 PXIe_SYNC100 GND PXIe_DSTARC PXIe_DSTARC GND 2 PRSNT PWREN GND PXIe_DSTARB PXIe_DSTARB GND PXIe_DSTARA PXIe_DSTARA GND 3 SMBDAT SMBCLK GND RSV RSV GND RSV RSV GND 4 MPWRGD PERST GND RSV RSV GND 1RefClk 1RefClk GND 5 1PETp0 1PETn0 G...

Страница 25: ...B C D E F 1 GND GA4 GA3 GA2 GA1 GA0 GND 2 GND 5Vaux GND SYSEN WAKE ALERT GND 3 GND 12V 12V GND GND GND GND 4 GND GND GND 3 3V 3 3V 3 3V GND 5 GND PXI_TRIG3 PXI_TRIG4 PXI_TRIG5 GND PXI_TRIG6 GND 6 GND PXI_TRIG2 GND ATNLED PXI_STAR PXI_CLK10 GND 7 GND PXI_TRIG1 PXI_TRIG0 ATNSW GND PXI_TRIG7 GND 8 GND RSV GND RSV PXI_LBL6 PXI_LBR6 GND ...

Страница 26: ...lp Patents in your software the patents txt file on your media or the National Instruments Patent Notice at ni com patents You can find information about end user license agreements EULAs and third party legal notices in the readme file for your NI product Refer to the Export Compliance Information at ni com legal export compliance for the National Instruments global trade compliance policy and ho...

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