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Register-Level Programming Appendix E
Lab-PC+ User Manual E-20 © National Instruments Corporation
To use the error interrupt, set the ERRINTEN bit in the Command Register 3. If this bit is set, an
interrupt is generated whenever the OVERFLOW or the OVERRUN bit in the Status Register is
set. This interrupt condition is cleared by writing to the A/D Clear Register.
Programming DMA Operation
The Lab-PC+ can be programmed so that the FIFO generates a DMA request signal every time
one or more A/D conversion values are stored in the FIFO. To program the DMA operation,
perform the following steps after the A/D circuitry is set up for a data acquisition operation and
before the data acquisition operation begins:
1. Set the DMAEN bit in Command Register 3 to enable DMA request generation.
2. Program the DMA controller to service DMA requests from the Lab-PC+ board. Because the
DMA transfer is an 8-bit operation, the transfer number written to the DMA Controller Count
Register should be twice the number of conversions.
3. If a DMA terminal count is received after the DMA service, writing to the DMATC Clear
Register clears the DMATC bit in the Status Register.
Once step 1 and step 2 are completed, the DMA controller automatically reads the FIFO Register
whenever an A/D conversion result is available and then stores the result in a buffer in memory
(the data type of the buffer can be 16-bit data).
A DMATC interrupt can be generated by a Lab-PC+ board. To use the DMA terminal count
interrupt, set the DMAEN and TCINTEN bits in Command Register 3. If these bits are set, an
interrupt is generated and the DMATC bit in the Status Register is set whenever the DMATC
pulse is detected. Writing to the DMATC Clear Register clears this interrupt condition.
Programming the Analog Output Circuitry
The analog output circuitry on the Lab-PC+ uses double-buffered DACs. Thus, the voltage at
the output pins (pins DAC0 OUT and DAC1 OUT on the Lab-PC+ I/O connector) does not have
to be updated immediately with each write to the DAC Data Registers. The analog output can be
updated in synchronization with Counter A2 output or the external update control signal
EXTUPDATE*. This ability is useful for waveform generation applications because the timed
update pulses eliminate the timing jitter associated with software writes to the DAC Data
Registers.
The voltage at the analog output circuitry pins (pins DAC0 OUT and DAC1 OUT on the
Lab-PC+ I/O connector) is controlled by loading the DAC in the analog output channel with a
12-bit digital code. The DACs can be loaded by writing the digital code to the DAC0 and DAC1
Data Registers (L and H). Writing to the DAC0 Data Register loads DAC0, and writing to the
DAC1 Data Register loads DAC1. The analog output on pins DAC0 OUT or DAC1 OUT can
be updated in one of three ways: immediately when the DAC0 or the DAC1 Data Register is
written to, when a low level is detected on the EXTUPDATE* pin, or when a low level is
detected on the output of Counter A (OUTA2). The LDAC bits in Command Register 2
determine which update method is used. If LDAC0 is set high, the analog output from DAC0 is