Chapter 4
Signal Connections
©
National Instruments Corporation
4-17
for the PFI2/CONVERT* pin. Be careful not to drive a PFI signal
externally when it is configured as an output.
As an input, you can individually configure each PFI for edge or level
detection and for polarity selection, as well. You can use the polarity
selection for any of the 13 timing signals, but the edge or level detection
will depend upon the particular timing signal being controlled. The
detection requirements for each timing signal are listed within the
section that discusses that individual signal.
In edge-detection mode, the minimum pulse width required is 10 ns.
This applies for both rising-edge and falling-edge polarity settings.
There is no maximum pulse-width requirement in edge-detect mode.
In level-detection mode, there are no minimum or maximum
pulse-width requirements imposed by the PFIs themselves, but there
may be limits imposed by the particular timing signal being controlled.
These requirements are listed later in this chapter.
DAQ Timing Connections
The DAQ timing signals are SCANCLK, EXTSTROBE*, TRIG1,
TRIG2, STARTSCAN, CONVERT*, AIGATE, and SISOURCE.
Posttriggered data acquisition allows you to view only data that is
acquired after a trigger event is received. A typical posttriggered DAQ
sequence is shown in Figure 4-8. Pretriggered data acquisition allows
you to view data that is acquired before the trigger of interest in addition
to data acquired after the trigger. Figure 4-9 shows a typical
pretriggered DAQ sequence. The description for each signal shown in
these figures is included later in this chapter.
Figure 4-8.
Typical Posttriggered Acquisition
1
3
0
4
2
TRIG1
STARTSCAN
CONVERT*
Scan Counter
PCI_E.book Page 17 Thursday, June 25, 1998 12:55 PM
