Index
I-6
©
National Instruments Corporation
pin assignments (figure), 4-2, B-2
polarity selection, analog input, 3-3 to 3-4
posttriggered data acquisition, 4-17
power connections
+5 V power pins, 4-15
self-resetting fuse, 4-15
power requirement specifications, A-9
pretriggered data acquisition, 4-17 to 4-18
programmable function inputs (PFIs). See
PFIs (programmable function inputs).
programmable gain instrumentation amplifier.
See PGIA (programmable gain
instrumentation amplifier).
Q
questions and answers
analog input and output, C-2 to C-3
general information, C-1 to C-2
installation and configuration, C-2
timing and digital I/O, C-3 to C-5
R
register-level programming, 1-4
requirements for getting started, 1-2
RTSI clocks, 3-12
RTSI trigger lines, 3-13
signal connection (figure), 3-13
specifications, A-8
S
SCANCLK signal
description (table), 4-3
signal summary (table), 4-6
timing connections, 4-18
signal connections
analog input, 4-8
analog output, 4-13
differential measurements, 4-9 to 4-12
common-mode signal rejection, 4-12
connection considerations, 4-10
floating signal sources, 4-9,
4-11 to 4-12
ground-referenced signal sources,
4-9, 4-11
nonreferenced signal sources,
4-11 to 4-12
recommended configuration
(table), 4-10
digital I/O, 4-13 to 4-14
field wiring considerations, 4-35 to 4-36
I/O connector, 4-1 to 4-7
exceeding maximum ratings
(warning), 4-1
I/O signal summary (table),
4-6 to 4-7
pin assignments (figure), 4-2, B-2
signal descriptions (table), 4-3 to 4-5
power connections, 4-15
RTSI trigger lines, 3-13
timing connections, 4-15 to 4-35
DAQ timing connections,
4-17 to 4-26
AIGATE signal, 4-25
CONVERT* signal,
4-23 to 4-25
EXTSTROBE* signal,
4-18 to 4-19
SCANCLK signal, 4-18
SISOURCE signal, 4-25 to 4-26
STARTSCAN signal,
4-22 to 4-23
TRIG1 signal, 4-19 to 4-20
TRIG2 signal, 4-20 to 4-21
typical posttriggered acquisition
(figure), 4-17
typical pretriggered acquisition
(figure), 4-18
PCI_E.book Page 6 Thursday, June 25, 1998 12:55 PM