Chapter 3
Signal Connections
3-26
©
National Instruments Corporation
•
82C53 digital output specifications (referenced to DGND):
–
V
oh
output logic high voltage
3.7 V min
—
–
V
ol
output logic low voltage
—
0.45 V max
–
I
oh
output source current, at V
oh
—
–0.92 mA max
–
I
ol
output sink current, at V
ol
—
2.1 mA max
Figure 3-16 shows the timing requirements for the GATE and CLK input
signals and the timing specifications for the 82C53 OUT output signals.
Figure 3-16.
General Purpose Timing Signals
The GATE and OUT signals in Figure 3-16 are referenced to the rising edge
of the CLK signal.
t
sc
t
pwh
t
pwl
t
gsu
t
gh
t
gwh
t
gwl
t
outc
t
outg
CLK
GATE
OUT
V
OH
V
IH
V
IL
V
IH
V
OL
V
IL
t
sc
t
pwh
t
pwl
t
gsu
t
gh
t
gwh
t
gwl
t
outc
t
outg
clock period
clock high level
clock low level
gate setup time
gate hold time
gate high level
gate low level
output delay from clock
output delay from gate
380 ns minimum
230 ns minimum
150 ns minimum
100 ns minimum
50 ns minimum
150 ns minimum
100 ns minimum
300 ns maximum
400 ns maximum
